Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-03-29
2003-09-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S738000
Reexamination Certificate
active
06620715
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for processing a semiconductor substrate.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabrication of an integrated circuit involves numerous processing steps. To form a metal-oxide-semiconductor (MOS) integrated circuit, for example, a gate dielectric, typically formed from silicon dioxide (“oxide”), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form source and drain regions. Such transistors may be connected to each other and to terminals of the completed integrated circuit using conductive interconnect lines. In addition, the fabrication of MOS transistors typically includes the formation of isolation structures between the active areas of the substrate. In general, the isolation structures may define the field regions of the semiconductor substrate, while the area including transistors may define the active areas of the substrate.
A technique known as “photolithography” is generally used to pattern various structures of an integrated circuit during its fabrication process. In general, photolithography entails transferring an optical image to a photosensitive film from a patterned mask plate (i.e., reticle) placed between the light source and the film. Such a process may include coating the photosensitive film, i.e., “photoresist” upon a semiconductor topography to be patterned. A mask plate having both opaque and transparent regions may be placed above the photoresist and radiation may be transmitted through the transparent regions of the mask plate to the photoresist. The solubility of resist exposed to the radiation is altered by a photochemical reaction. Subsequently, a solvent may be used to remove the resist areas of higher solubility. The resulting patterned resist film may serve to protect underlying conductive or dielectric material from etching processes or ion implantation. Consequently, structures of an integrated circuit may be formed having a similar lateral layout to the pattern of the overlying photoresist. In some embodiments, an anti-reflective layer may be interposed between the photoresist and the semiconductor topography in order to prevent the reflection of energy rays. Such a reflection of rays may undesirably alter the pattern of the photoresist by exposing additional portions of the photoresist. In addition or alternatively, the reflected energy rays may produce standing waves within the photoresist during exposure and result in an undesirably ragged post-develop photoresist profile.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Smaller feature sizes may allow more transistors to be placed on a single substrate. In addition, transistors with smaller feature sizes may function faster and at a lower threshold voltage than transistors having larger feature sizes. The feature sizes of a transistor, however, may be limited by the image resolution of the photolithographic equipment used to form the transistor. Such image resolution is typically dependent on the wavelength of the photolithographic tool. For example, the minimum resolvable feature size of a 248 nm photolithographic tool may be approximately 0.14 microns. As such, in order to obtain a structure with a feature size with a dimension smaller then approximately 0.14 microns, a smaller wavelength photolithographic tool may need to be used.
However, there are disadvantages with using smaller wavelength photolithographic tools. For example, photolithographic tools are typically expensive and therefore, purchasing new photolithographic tools for each new development of transistors with reduced feature sizes may be cost prohibitive. Furthermore, smaller wavelength photolithographic tools used to produce such transistors may require substantial process development to produce such small feature sizes. In addition, the materials used for photoresist films and underlying anti-reflective layers may be dependent on the wavelength used with the photolithographic tool and therefore, may need to be revised for consistency with the new photolithographic tools. In some cases, problems, such as poor image resolution, poor etch selectivity, or patterning clarity such as line edge roughness, may arise with such immature technologies and chemistries. As a result, the installation of new photolithographic equipment and its associated chemistry may delay the development of transistors of reduced feature sizes.
One method of producing transistor structures with dimensions smaller than the dimensions obtainable by a photolithographic tool used to pattern the structure is sometimes referred to as “trimming.” “Trimming” typically includes etching the periphery of a patterned structure underlying a photoresist layer such that dimensions of the structure are reduced. Such a technique typically reduces the length and width of the patterned structure. However, a reduction in both the length and the width may be undesirable in some cases. For example, during the fabrication of gate structures, it may be desirable to reduce the width of a gate structure in order to decrease the channel length of the subsequently formed transistor. However, each end of the gate structure typically needs to extend partially over an isolation region in order to prevent a short from occurring between the gate's source and drain regions. Unfortunately, “trimming” may undesirably shorten the length of the gate structure such that one or more of its ends no longer extends over an isolation region. As a result, the subsequently formed transistor may have decreased performance or in some cases may fail to function. In some cases, the transistor fabrication process may require forming larger isolation regions to separate active areas of the transistor in order to insure that the ends of the subsequently trimmed gate structure extend over isolation regions. Such an embodiment may undesirably reduce the active area of the wafer. Consequently, fewer transistors may be fabricated on a single wafer, thereby reducing the advantage of reducing the feature size of the transistor.
It would, therefore, be advantageous to develop a method for forming a semiconductor structure with a dimension smaller than what is obtainable by the photolithographic equipment used to fabricate the structure. In particular, it would be advantageous to develop such a method that does not undesirably reduce one or more other dimensions of the structure.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a method for processing a semiconductor topography. In particular, a method is provided for forming device components laterally spaced within a semiconductor topography. More specifically, a method is provided for fabricating a device, which includes device components and one or more spacings there between that may each have a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components. In particular, the method may be used to form a spacing that has a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components arranged adjacent to the spacing. In some embodiments, the method may be used to form device components and spacings there between that are arranged along a first dimension parallel to an underlying substrate of the semiconductor topography.
The method may include, for example, patterning an upper layer of the semiconductor topography using a photolithography process to form a first feature having dimensions substantially equal t
Blosse Alain P.
Chowdhury Saurabh Dutta
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Lindsay Jr. Walter L.
Niebling John F.
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