Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-07
2003-05-06
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06559501
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacturing of semiconductor devices in general, and in particular, to a method of fabricating a split-gate flash memory cell having salicided control gate and self-aligned contact.
(2) Description of the Related Art
For complementary metal-oxide semiconductor (CMOS) technology with feature sizes less than 0.35 micrometer (&mgr;m), it is becoming more and more essential to employ salicidation processes in order to reduce the electrical resistance of device contacts which are dramatically shrinking in size. This follows from the well-known inverse-relationship of resistance to area. At the same time, and commensurate with the scaling down of very large scale (VLSI) and ultra scale integrated (ULSI) devices, it is also becoming essential to employ self-alignment process for forming contacts in the memory cells. Salicidation process is itself a self-aligned silicidation process as will be described below, and the self-aligned contact (SAC) of the memory cell has different requirements than the salicide contacts in the peripheral circuits of a semiconductor memory chip. The salicidation and the SAC processes are usually incompatible. However, a novel process is disclosed in the present invention where the two processes are successfully integrated. To help in the understanding of the invention, some memory cell types and the salicidation process will now be described.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Generally, flash EEPROM cells having both functions of electrical programming and erasing may be classified into two categories, namely, a stack-gate structure and a split-gate structure. A conventional stack-gate type cell is shown in
FIG. 1
a
where, as is well known, tunnel oxide film (
20
′), a floating gate (
30
′), an interpoly insulating film (
40
′) and a control gate (
50
′) are sequentially stacked on a silicon substrate (
10
) between a drain region (
13
′) and a source region (
15
′) separated by channel region (
17
′). Substrate (
10
) and channel region (
17
′) are of a first conductivity type, and the first (
13
′) and second (
15
′) doped regions are of a second conductivity type that is opposite the first conductivity type.
One of the problems that is encountered in flash memory of
FIG. 1
a
is the “over-erasure” of the cell contents during erasure operations. In
FIG. 1
a
, the stacked-gate transistor is capable of injecting electrons from drain (
13
′), based on a phenomenon known as the Fowler-Nordheim Tunneling Effect, through tunneling oxide layer (
20
′) into floating gate (
30
′). The threshold voltage of a stacked-gate transistor can be raised by means of such electron injection, and the device is then assumes a first state that reflect the content of the memory cell. On the other hand, during erasure of the memory cell, electrons are expelled from the source (
15
′) through tunneling oxide layer (
20
′) and out of floating gate (
30
′) of the transistor. As a result of this electron removal, the threshold voltage is lowered and thus the device then assumes a second memory state.
During the process of memory content erasure, however, to ensure complete removal of the electrons previously injected, the erasure operation is normally sustained for a slightly prolonged time period. There are occasions when such a prolonged erasure operation results in the removal of excess electrons, i.e., more electrons than were previously injected. This results in the formation of electron holes in the floating gate of the device. In severe cases, the stacked-gate transistor becomes a depletion transistor, which conducts even in the absence of the application of a control voltage at the control gate, (
50
′). This phenomenon is known in the art as memory over-erasure.
To overcome the described memory over-erasure problem of stacked-gate type EEPROM devices, a split-gate EEPROM device is used as shown in
FIG. 1
b
. This memory device comprises floating-gate transistor which similarly includes control gate (
50
), floating gate (
30
) with an intervening interpoly oxide (
40
) as in the case of the stacked-gate transistor of
FIG. 1
a
. As is usual, gate-oxide (
20
) separates the floating gate from the substrate. A poly-oxide layer (
33
) is also usually formed for use as a hard-mask in forming the floating gate (
30
). However, floating gate (
30
) here covers only a portion of the channel region, (
17
), and the rest of the channel region, (
19
), is directly controlled by control gate (
50
). This split-gate-based memory cell is equivalent to a series connected floating-gate transistor (
17
) and an enhanced isolation transistor (
19
), as is schematically represented in
FIG. 1
b
. The principal advantage of such configuration is that isolation transistor (
19
) is free from influence of the state of floating gate (
17
) and remains in its off-state, even if floating-gate transistor (
17
) is subjected to the phenomenon of over-erasure and therefore, is in a conductive state. The memory cell can thus maintain its correct state irrespective of the over-erasure problem.
In the fabrication of a split-gate flash memory cell such as shown
FIG. 1
b
, it would desirable to use a conventional salicide (self-aligned silicide) process for source/drain contact over regions (
13
) and/or (
15
). But that is not possible as will be explained later. The need for salicidation arises from the controlling effect that the physical structure and the electrical characteristics of gate electrode (
30
) have on the operation of the memory device. Its forming is usually complex and requires exacting processes. Furthermore, materials used for the gate must be compatible with processes that follow up to the completion of the manufacture of the semiconductor devices. With the advent of ULSI (ultra large scale integration) of devices, the shrinking dimensions of the gate as well as the materials used to form the gates have gained even more significance. Thus, if aluminum were to be used as the gate material for example, then, because of its low melting point, it would have to be deposited following the completion of all high-temperature process steps, including drive-in of the source and drain regions. To form the gate electrode in proper relationship to the source/drain, it must be separately aligned with respect to the source and drain. This alignment process adversely affects both packing density and parasitic overlay capacitances between the gate and source/drain regions. For these reasons, it has become a recent practice to use polycrystalline silicon (poly-Si), which has the same high melting point as the silicon substrate, as the gate material. Hence, polysilicon can now be deposited over the gate to form the gate electrode prior to the source and drain formation. Consequently, the gate itself can serve as a mask during formation of the source and drain regions by either diffusion or ion implantation, as is known in the art. Gate (
30
) thereby becomes nearly perfectly aligned over channel (
17
) and with respect to source (
13
) shown in
FIG. 1
b
. The only overlap of the source and drain is due to lateral diffusion of the dopant atoms. This self-alignment feature simplifies the fabrication sequence, increases packing density, and reduces the gate-source and gate-drain parasitic overlap capacitances. For completeness, we note that the threshold voltage, V
th
, of MOS device is also favorably affected by the use of polysilicon as the gate electrode material.
On the other hand, polysilicon has much higher electrical resistance as compared to aluminum, for example, and the miniaturization of devices in the ULSI era has exacerbated the electrical properties of the poly-Si gate electrode. Polysilicon is commonly doped by ion implantatio
Hsieh Chia-Ta
Kuo Di-Son
Sung Hung-Cheng
Ackerman Stephen B.
Hoang Quoc
Nelms David
Oktay Sergin
Saile George O.
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