Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-02
2003-03-04
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S649000, C438S655000
Reexamination Certificate
active
06528421
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method for forming silicide, and particularly relates to a method for forming silicide lines with low sheet resistance and high thermal stability.
2. Description of the Prior Art
Because silicide has many advantages such as low sheet resistance, low contact resistance to silicon, good adhesion on silicon, and low stress, silicide has been widespreadly used to metal contact, gate line, and other silicide structures.
Fabrication of silicide could be briefly divided into two categories: one category is that directly deposits silicide on substrate and then forms required silicide structures by performing a pattern process; another category is that forms metal layer on silicon substrate, next, performs thermal process to let silicide layer is formed. Moreover, because not each kind of silicide can be formed by deposition, the latter category is more popular than the former category. Especially, distribution of silicide layer can be controlled by predetermining distribution of silicon layer and then pattern process is not necessary, this is so-called self-aligned silicide fabrication.
Salicide is thermally formed by reaction of metal and silicon, agglomeration phenomenon almost is inevitable, especially when temperature is higher or thermal period is longer in the sequent process steps. And occurrence of agglomeration usually induces some problems, such as junction leakage, necking of silicide line, open of silicide line, and resistance increase of silicide. Refers to two indication figures:
FIG. 1A
which shows agglomeration phenomenon is not occurred and
FIG. 1B
which shows agglomeration phenomenon is occurred, where semiconductor structure
11
locates on substrate
10
and silicide
12
locates on semiconductor structure
11
. Researches discover that agglomeration is related to both structure recombination and phase transformation of silicide layer, and then sheet resistance of thicker and wider silicide structure is hardly degraded by agglomeration phenomenon than that of thinner and narrower silicide structure. In other words, thermal stability of silicide structure is proportional to thickness and width of silicide structure.
Therefore, because scale of silicide structure must be getting decreased whenever critical scale of semiconductor structure is continually decreased, it is indisputable that agglomeration phenomenon is an inevitable problem of silicide structure, especially silicide line which both width and thickness are severely limited.
Besides, owing to structure of semiconductor device is continually complex, silicide lines usually are not formed on a smooth surface but are formed on a rugged semiconductor structure with steps and corners. Under the present circumstances, stress of silicide on corners of semiconductor structure is larger than stress of silicide on flat of semiconductor structure, and then silicide film do not tend to agglomerate on corners during subsequent thermal processes, such that decreased cross-sectional area of silicide line and broken silicide line are unavoidable. Besides, the physical vapor deposited metal film is hard to be conformally formed on the sidewalls of silicon steps, which makes the metal layer thinner at sidewalls. Consequently, the formed silicide is thinner at structure sidewalls. Refers to FIG.
1
C and
FIG. 1D
, where silicon layer
13
is essentially conformal but metal layer
14
is not conformally formed on sidewall of hole
15
, and then formed thickness of silicide
12
on sidewall is less than that of silicide
12
on flat part of structure.
Accordingly, thermal stability of silicide line is degraded by decreasing the line width, the aggressive topography underneath the silicide line and the thickness uniformity of silicide lines. It is desired to develop a method for improve above disadvantages, such that silicide structure, especially silicide line, could be further used by very large scale integration (VLSI) and ultra large scale integration (ULSI).
SUMMARY OF THE INVENTION
One main object of the invention is to reduce or even eliminate the effect of agglomeration phenomenon on silicide.
Another object of the invention is to present a method for forming silicide lines, where silicide lines are formed on a rugged surface.
Still an essential object of the invention is to present a method for enhancing thermal stability of silicide without obviously modifying well-known fabrication procedure of silicide.
Further, another main object of the invention is to present a suitable method for forming silicide line with small critical dimension.
One preferred embodiment of this invention is a method for forming silicide. Provide a substrate which is covered by a semiconductor structure with a rugged topography, and form a silicon layer on the semiconductor structure, where the topography of the silicon layer is similar to the rugged topography. Etch the silicon layer such that the topography of the silicon layer is curved, and form a metal layer on the silicon layer. Finally, perform a thermal process such that a silicide layer is made from both the metal layer and the silicon layer, where the suicide layer could be used to form numerous silicide lines.
Another preferred embodiment of this invention also is a method for forming silicide. Provide a substrate with a rugged first surface and etch the substrate such that the rugged first surface is changed into a curved second surface. Form a silicon layer on the second surface, where the topography of the silicon layer is similar to the topography of the second surface. Form a metal layer on the silicon layer; and perform a thermal process such that a silicide layer is made from both the metal layer and the silicon layer, where the silicide layer could be used to form numerous silicide lines.
REFERENCES:
patent: 5510296 (1996-04-01), Yen et al.
patent: 5824586 (1998-10-01), Wollesen et al.
patent: 6221762 (2001-04-01), Byun et al.
patent: 6346466 (2002-02-01), Avanzino et al.
Macronix International Co. Ltd.
Nguyen Tuan H.
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