Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-11
2001-12-25
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S197000, C438S299000, C438S655000, 43, 43, 43
Reexamination Certificate
active
06333262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming silicide on a semiconductor wafer, and more particularly, to a method for forming silicide while simultaneously preventing impurities in a doped silicon layer from outgassing during rapid thermal processing steps.
2. Description of the Prior Art
Metal-oxide-semiconductor (MOS) transistors are important components of semiconductor circuits, and the electrical performance of the gate in the MOS transistor is an important issue that effects the quality of MOS transistors. The prior art gate typically includes a doped polysilicon layer or a doped amorphous silicon layer used as the main conductive layer, and a silicide layer stacked on the conductive layer. The silicide layer provides a good ohmic contact to the devices of the MOS transistor, thus reducing sheet resistance and enhancing the operational speed of the MOS transistor.
Please refer to
FIG. 1
to FIG.
3
.
FIG. 1
to
FIG. 3
are schematic diagrams of the method for forming silicide
28
on a semiconductor wafer
10
according to the prior art. As shown in
FIG. 1
, the semiconductor wafer
10
includes a substrate
12
. The substrate
12
shown in
FIG. 1
is used to form a MOS transistor, and the silicide
28
is a portion of the gate electrode of the MOS transistor. The substrate
12
includes a gate oxide
14
, a doped polysilicon layer
16
stacked on the gate oxide
14
, and two spacers
18
formed adjacent to the gate
17
. In the prior art method, a thin film deposition process is performed to form a cobalt layer
22
on the substrate
12
and the gate
17
. A titanium nitride (TiN) layer
24
is then deposited on the cobalt layer
22
using a sputtering method.
As shown in
FIG. 2
, a rapid thermal processing (RTP) step is performed, the process temperature between 720° C. and 760° C., to make portions of the cobalt layer
22
react with silicon inside the doped polysilicon layer
16
and inside the silicon substrate
12
around the gate
17
so as to form a transitional silicide
26
. The transitional silicide is a cobalt-rich silicide, such as CoSi or Co
2
Si. The titanium nitride layer
24
and the portions of the cobalt layer
22
that have not reacted with the silicon are then removed.
Another rapid thermal processing step is then performed, the process temperature between 830° C. and 870° C., to make the transitional silicide
26
react with portions of the doped silicon layer
16
and the silicon substrate
12
so as to form the cobalt silicide (CoSi
2
)
28
that is much more stable and which has a low resistance. Finally, a chemical vapor deposition (CVD) process is performed to form a dielectric layer
29
of silicon dioxide, which covers the gate
17
, as shown in FIG.
3
.
Because there is no barrier layer or passivation layer covering the transitional silicide
26
during the second rapid thermal processing step, impurities, such as arsenic or phosphorus, in the doped polysilicon layer
16
will outgass during the rapid thermal processing step. This results in an impurity dosage in the doped polysilicon layer
16
that is less than the predetermined dosage, and affects the conductive capability and electrical performance of the gate electrode. In addition, a portion of the impurities outgassing from the doped polysilicon layer adhere to the surface of the chamber of the rapid thermal processing machine, which can contaminate or even harm the machine.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method for forming silicide on a semiconductor wafer so as to solve the above mentioned problems.
In the preferred embodiment of the present invention, the semiconductor wafer includes a doped silicon layer on a predetermined area of the semiconductor wafer, a cobalt (Co) layer positioned on the doped silicon layer, and a titanium nitride (TiN) layer covering the cobalt layer. A first rapid thermal processing (RTP) step is first performed to make portions of the metal layer react with silicon inside the doped silicon layer so as to form a transitional silicide, CoSi or Co
2
Si. The titanium nitride layer and the portions of the cobalt layer that have not reacted with the silicon are then removed. A dielectric layer is formed on the transitional silicide. Finally, a second rapid thermal processing (RTP) step is performed to make the transitional silicide react with portions of the doped silicon layer so as to form the silicide.
In another embodiment of the present invention, a first rapid thermal processing (RTP) step is initially performed to make portions of the metal layer react with silicon inside the doped silicon layer so as to form a transitional silicide, CoSi or Co
2
Si. The titanium nitride layer and the portions of the cobalt layer that have not reacted with the silicon are then removed. A barrier layer of an optional material is formed on the transitional silicide. A second rapid thermal processing (RTP) step is performed to make the transitional silicide react with portions of the doped silicon layer so as to form the cobalt silicide (CoSi
2
). Finally, the barrier layer is removed, and a dielectric layer is formed on the surface of the cobalt silicide.
The dielectric layer or the barrier layer is deposited on the transitional silicide before the second rapid thermal processing step in the present invention to prevent the impurities in the doped polysilicon layer from outgassing during the rapid thermal processing step. Therefore, the conductive capability and electrical performance of the gate electrode is ensured.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 4729969 (1988-03-01), Suda et al.
patent: 5236865 (1993-08-01), Sandhu et al.
patent: 5543359 (1996-08-01), Horiuchi
patent: 5851921 (1998-12-01), Gardner et al.
patent: 6187617 (2001-02-01), Gauthier, Jr. et al.
patent: 6204132 (2001-03-01), Kittl et al.
Chang Ruoh-Haw
Chen Shu-Jen
Tseng Kuen-Syh
Elms Richard
Hsu Winston
Luu Pho
United Microelectronics Corp.
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