Method for forming shallow trench isolation structures

Details Method for forming shallow trench isolation structures Method for forming shallow trench isolation structures

2000-06-06

2002-03-19

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S180000, C438S392000, C438S424000

Reexamination Certificate

active

06358785

ABSTRACT:

TECHNICAL FIELD
The present invention relates most generally to semiconductor devices and methods for forming the same. More particularly, the present invention relates to a method for forming shallow trench isolation (STI) structures.
BACKGROUND OF THE INVENTION
In today's advancing semiconductor manufacturing processing technology, the multitude of components which combine to form an integrated circuit device are being formed in increasingly closer proximity. In order to avoid adjacent devices from shorting to one another, and in order to avoid leakage between devices formed in close proximity to one another, STI structures have become a commonly used feature in the semiconductor manufacturing industry.
STI structures are typically formed by producing a trench-like opening in a substrate, then filling the trench-like opening with an insulating material. The insulating materials may be formed by various chemical vapor deposition (CVD) techniques such as low pressure chemical vapor deposition (LPCVD), high density plasma (HDP) deposition, or any other suitable method for depositing an insulating material within a trench opening. After the opening is filled with a deposited insulating material, a planarizing process such as chemical mechanical polishing is used to planarize the structure by removing any portions of the insulating material which are formed above the upper plane beneath which the trench opening extends.
Nitride (silicon nitride—Si
3
N
4
) or other oxidation resistant, and suitably hard films, are typically used as films which form the upper surface beneath which the trench opening extends. Hard films are favored because of their resistance to polishing during the polishing operations used to planarize the STI structures. Such films have relatively low polishing rates and may be referred to as polishing-stop layers.
During the formation of STI structures, problems arise when the polishing operations used to planarize the STI structure cause “dishing” on the top of the STI structure. Dishing describes the phenomena wherein the top surface of the insulating material within the trench becomes recessed below the upper surface of the polishing-stop layer such as silicon nitride. Dishing results because the deposited insulating materials which are formed by any of various CVD techniques to fill the trenches, have a higher polishing rate than the polishing-stop layers used. In order to ensure complete removal of the deposited insulating material from over the polishing-stop layer, a sufficient amount of polishing is used which results in the upper surface of the deposited insulating material becoming recessed within the trench and below the surface of the polishing-stop layer.
As a result of dishing, the central portion of the top surface of the STI structure is typically recessed below the peripheral portion of the top surface of the STI structure. The peripheral edges of the insulating material within the trench generally extend up the side of the trench opening to intersect the upper surface of the polishing-stop layer at the edges of the trench opening. Sharp, upward projections may therefore result at these peripheral edges. The central portion of the top surface of the STI structure may be recessed by as many as 500 angstroms with respect to the edges of the STI structure due to dishing. After the nitride polishing-stop layer is subsequently removed and the entire top portion of the STI structure uniformly recessed, the 500 angstrom height difference remains on the top of the STI structure.
After the STI structure is completed, the sharp, upward projections may also remain at the edges of the STI structure which may additionally extend above the upper surface of the semiconductor substrate. These projections may extend above the bulk of the STI structure by as much as 500 angstroms, and may extend above the surrounding semiconductor substrate by an even greater distance. Polysilicon films are commonly used to form transistor gates and to serve other interconnection functions in semiconductor integrated circuits. At the location where the polysilicon film extends over the sharp upward projections created at the peripheries of STI structures due to dishing, a localized electric field is created. The same is true when semiconductor materials other than polysilicon, are used as interconnection materials. Such a localized electric field is highly undesirable as it may produce various electrical parametric problems throughout the device. For example, such an electric field formed in a transistor gate may significantly lower the threshold voltage, V
t
, for a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device. These sharp, upward projections in the STI structure created by dishing can cause other electrical problems which may result in device failure, or which may require additional implants to compensate for changed parametric characteristics, or both.
It can therefore be seen that there is a need for a process for forming shallow trench isolation structures having planar upper surfaces and which do not exhibit dishing-related problems.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention addresses the shortcomings of the processes for forming shallow trench isolation structures known to the prior art and provides an improved process for forming superior shallow trench isolation structures which do not exhibit dishing related problems. The present invention describes materials, processes, and structures used to produce low leakage STI structures having substantially planar upper surfaces. The present invention provides a method for employing a silicon film as the trench fill material, then polishing the silicon film in its as-deposited or oxidized form. The silicon or oxidized silicon material has a polishing rate which is more similar to that of the film used as the polishing-stop layer than an insulating film deposited using conventional CVD methods. As such, the polishing operation produces a material within the trench having a substantially planarized upper surface. If the silicon is polished in its as-deposited form, a subsequent oxidation step is used to convert the silicon material to a silicon dioxide material using principles similar to LOCOS oxidation. The production of shallow trench isolation structures having planar upper surfaces precludes the subsequent formation of localized electric fields and therefore produces devices which are less prone to leakage and other parametric failures.
It is to be understood that both the foregoing general description and the following detailed descriptions are exemplary, but not restrictive of the invention.


REFERENCES:
patent: 4318751 (1982-03-01), Horng
patent: 5010039 (1991-04-01), Ku et al.
patent: 5316978 (1994-05-01), Boyd et al.
patent: 5364810 (1994-11-01), Kosa et al.
patent: 5618745 (1997-04-01), Kita
patent: 5918130 (1999-06-01), Hause et al.
patent: 6207494 (2001-03-01), Graimann et al.

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