Method for forming shallow trench isolation

Details Method for forming shallow trench isolation Method for forming shallow trench isolation

2002-12-17

2004-06-01

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S435000, C438S702000

Reexamination Certificate

active

06743728

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor process, and more particularly to a shallow trench isolation fabricated process using high density plasma chemical vapor deposition (HDPCVD).
2. Description of the Related Art
Recently, as the manufacturing techniques of semiconductor integrated circuits develop, the number of elements in a chip increase. The size of the element decreases as the degree of integration increases. The line width used in manufacturing lines has decreased from sub-micron to quarter-micron, or even to a smaller size. However regardless of the reduction of the size of the element, adequate insulation or isolation must be formed among individual elements in the chip so that good element characteristics can be achieved. This technique is called device isolation technology. The main object is to form an isolation region, and reduce the size of the isolation as much as possible while assuring good isolation to provide more space for additional elements.
Among different element isolation techniques, LOCOS and shallow trench isolation region manufacturing methods are the two used most. In particular, as the latter has a small isolation region and can keep the substrate level after the process is finished, it is the semiconductor manufacturing method obtaining the most attention. In the conventional shallow trench isolating method, a dielectric layer is formed in the trench within the substrate using a chemical vapor deposition (CVD) Afterwards, the excess portion of the dielectric layer over the substrate is removed by etching or chemical mechanical polishing (CMP). Thereby a shallow trench isolation is formed. However, due to that scaled down density and dimensions of integrated circuits (ICs), i.e., 0.11 micron or deeper, the dielectric layer cannot easily fill the entire trench, thereby decreasing the efficiency of the element isolation.
As a result of filling the entire trench which has a high aspect ratio, recently, a high-density plasma chemical vapor deposition (HDPCVD) is used to form a dielectric layer on the substrate instead of chemical vapor deposition (CVD). In a HDPCVD, the dielectric layer is deposited using O2 and SiH4 gases.
FIGS.
1
A~
1
C show a conventional fabrication process of a shallow trench isolation. In
FIG. 1A
, a pad oxide layer
12
is deposited on a substrate
10
such as Si substrate, wherein the thickness of the pad oxide layer
12
is about 50~200 Å. The pad oxide layer
12
is formed using thermal oxidation or chemical vapor deposition (CVD). Thereafter, a silicon nitride layer
14
is deposited on the pad oxide layer
12
using CVD, and the thickness of the silicon oxide layer
14
is 500~2000 Å. A mask layer thereby consists of the pad oxide layer
12
and the silicon nitride layer
14
. Next, a pattern is defined on the silicon nitride layer
14
and the pad oxide layer using photolithography and etching techniques to expose a portion of the substrate
10
where the shallow trench isolation is formed.
Next, In
FIG. 1B
, the exposed portion of the substrate is etched to form a trench
15
, and the depth of the trench
15
is about 3500~5000 Å. Then, a thin liner layer
16
is formed on the sidewall of the trench
15
using thermal oxidation process, and the thickness of the liner layer
16
is 180 Å.
As shown in
FIG. 1C
, in a HDPCVD, a dielectric layer
18
is deposited and fills the trench
15
, wherein O2 and SiH4 are reactants.
As shown in
FIG. 2
, due to that the aspect ratio of the trench
15
being
4
and above, the dielectric layer
18
deposed on the silicon nitride layer
14
may cover the opening of the trench
15
in the high-density plasma chemical vapor deposition (HDPCVD) process, such that the dielectric layer
18
cannot fill the trench
15
completely, and a void is formed in the trench.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method for fabricating shallow trench isolation to improve dielectric layers in trenches. First, a substrate is provided. A mask layer is formed on the substrate. The mask layer is etched to expose a portion of the substrate, and the portion of the substrate is etched to form a trench. A liner layer is formed on the inside wall of the trench. A first dielectric layer and a sacrificial layer are sequentially deposited on the substrate such that the trench is substantially filled, wherein the first dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). A portion of the first dielectric layer is removed from the trench. The sacrificial layer is completely removed, and the aspect ratio of the trench is reduced. A second dielectric layer is deposited on the substrate such that the trench is substantially filled without voids, wherein the second dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). A portion of the second dielectric layer is removed from the trench.
Accordingly, another object of the present invention is to provide a method for fabricating shallow trench isolation using a boron-doped phosphosilicate glass (BPSG) layer as a sacrificial layer. During HDPCVD, the sacrificial layer is deposited so that the aspect ratio of the trench is reduced, and the dielectric fills the trench easily, wherein the BPSG layer is deposited by sub-atmospheric pressure chemical vapor deposition (SAPCVD) or atmospheric pressure chemical vapor deposition (APCVD), and the BPSG layer is planarized by a flow process to fill voids in the trench. Because boron-doped phosphosilicate glass is a dielectric material, the BPSG layer can remain in the trench as a portion of the dielectric layer.
According to the present invention, the dielectric layer can be deposited by HDPCVD in the high aspect ratio trench.


REFERENCES:
patent: 6150238 (2000-11-01), Wu et al.
patent: 6337282 (2002-01-01), Kim et al.
patent: 6531377 (2003-03-01), Knorr et al.
patent: 2003/0224580 (2003-12-01), Huang et al.

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