Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-02-15
2003-12-02
Fahmy, Jr., Wael (Department: 2814)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S701000, C438S740000, C257S153000, C257S329000
Reexamination Certificate
active
06656845
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for forming, with enhanced performance, semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices and over which are formed patterned conductor layers which are separated by dielectric layers.
As semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor device dimensions have decreased, it has become increasingly important in the art of semiconductor integrated circuit microelectronic to form within semiconductor integrated circuit microelectronic fabrications semiconductor devices with enhanced performance.
While semiconductor devices with enhanced performance are clearly desirable in the art of semiconductor integrated circuit microelectronic fabrication and often essential in the art of semiconductor integrated circuit microelectronic fabrication, semiconductor devices with enhanced performance are nonetheless not always readily fabricated within the art of semiconductor integrated circuit microelectronic fabrication. In that regard, semiconductor devices are often difficult to fabricate with enhanced performance within the art of semiconductor integrated circuit microelectronic fabrication insofar as it is often inherent within various types of semiconductor devices that fabricating those semiconductor devices with decreased dimensions will compromise performance of those semiconductor devices.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to fabricate semiconductor devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed within the art of semiconductor integrated circuit microelectronic fabrication for forming, with desirable properties, semiconductor devices within semiconductor integrated circuit microelectronic fabrications.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Kim, in U.S. Pat. No. 5,262,337 (a method for forming a metal oxide semiconductor field effect transistor (MOSFET) device absent a high horizontal electric field within a pair of lightly doped source/drain regions formed therein, by forming the metal oxide semiconductor field effect transistor (MOSFET) device within and upon a pillar within a semiconductor substrate whose pillar top comprises a channel region and whose pillar sidewalls comprise a pair of lightly doped source/drain regions, and wherein the pillar is surrounded by an “n” shaped gate electrode which in turn separates a pair of heavily doped source/drain regions formed within the semiconductor substrate adjacent the pillar); (2) Lur et al., in U.S. Pat. No. 5,292,680 (a method for forming a charge coupled device (CCD) with an enhanced transfer efficiency by forming the charge coupled device (CCD) with a series of gate electrodes formed upon a series of plateaus within a corrugated semiconductor substrate); and (3) Krivokapic, in U.S. Pat. No. 6,153,454 (a method for forming a metal oxide semiconductor field effect transistor (MOSFET) device with enhanced performance by forming the metal oxide semiconductor field effect transistor (MOSFET) device within a convex shaped semiconductor substrate such that a pair of source/drain regions slopes downwardly from a channel region within the metal oxide semiconductor field effect transistor (MOSFET)).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods and materials which may be employed in the art of semiconductor integrated circuit microelectronic fabrication for forming semiconductor devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming a semiconductor device within a semiconductor integrated circuit microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the semiconductor device is formed with enhanced performance.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a semiconductor substrate.
To practice the method of the present invention, there is first providing a semiconductor substrate. There is then formed over the semiconductor substrate a mask layer. There is then etched the semiconductor substrate while employing the mask layer as an etch mask layer to form an elevated plateau within an etched semiconductor substrate which separates a pair of isolation trenches within the etched semiconductor substrate. There is then laterally etched the mask layer to form a laterally etched mask layer formed upon the elevated plateau and laterally recessed from the pair of isolation trenches. Finally, there is then thermally oxidized the etched semiconductor substrate while employing the laterally etched mask layer as an oxidation mask layer to form from the elevated plateau a continuously curved convex elevated region within a thermally oxidized etched semiconductor substrate.
Within the present invention, and incident to further processing of the thermally oxidized etched semiconductor substrate having formed therein the continuously curved convex elevated region, there may be formed a semiconductor device with enhanced performance insofar as the semiconductor device may be formed within and upon the continuously curved convex elevated region.
The present invention provides a method for forming a semiconductor device within a semiconductor integrated circuit microelectronic fabrication, wherein the semiconductor device is formed with enhanced performance.
The present invention realizes the foregoing object by forming within a semiconductor substrate a continuously curved convex elevated region such that the semiconductor device may be formed within and upon the continuously curved convex elevated region with the semiconductor substrate.
The method of the present invention is readily commercially implemented.
As will be illustrated in greater detail within the context of the Description of the Preferred Embodiment, as set forth below, the present invention employs methods and materials as are otherwise generally conventional in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific process ordering to provide the method of the present invention. Since it is thus at least in part a specific process ordering of a series of methods which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
REFERENCES:
patent: 4512073 (1985-04-01), Hsu
patent: 4689872 (1987-09-01), Appels et al.
patent: 4965648 (1990-10-01), Yang et al.
patent: 5262337 (1993-11-01), Kim
patent: 5292680 (1994-03-01), Lur et al.
patent: 5382538 (1995-01-01), Zambrano et al.
patent: 5731604 (1998-03-01), Kinzer
patent: 5795793 (1998-08-01), Kinzer
patent: 5907169 (1999-05-01), Hshieh et al.
patent: 5981354 (1999-11-01), Spikes et al.
patent: 6005375 (1999-12-01), van Saders et al.
patent: 6110827 (2000-08-01), Chien et al.
patent: 6153454 (2000-11-01), Krivokapic
patent: 6259135 (2001-07-01), Hsu et al.
patent: 6287904 (2001-09-01), Lee et al.
patent: 2002/
Lee Hsin Yi
Wang Yin-Pin
Fahmy Jr. Wael
Rao Shrinivas H
Taiwan SEmiconductor Manufacturing Co., Ltd
Tung & Associates
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