Method for forming semiconductor memory device having a fuse

Details Method for forming semiconductor memory device having a fuse Method for forming semiconductor memory device having a fuse

2002-10-29

2003-11-04

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S132000, C438S215000, C438S233000, C438S281000, C438S631000, C438S645000

Reexamination Certificate

active

06642135

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2002-7695, filed on Feb. 9, 2002, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to method of fabricating a semiconductor device and, more specifically, to a dynamic random access memory (DRAM) device having a fuse.
BACKGROUND OF THE INVENTION
A DRAM device comprises a cell array area and a peripheral circuit area. The cell array area includes a plurality of unit cells, each of which comprises a MOS transistor and a storage capacitor. The peripheral circuit area consists of semiconductor circuits that control operations and input/output of the unit cells, for example a driver, a buffer or an amplifier. The peripheral circuit area usually includes a plurality of fuses, which can be cut by using a laser.
In continuing the trend of higher memory capacity, three-dimensional capacitors have been proposed in an attempt to increase an effective capacitor area in the unit cell. The three-dimensional capacitors have, for example, concave type or cylinder type storage electrodes. The heights of the three-dimensional capacitors are relatively high, as much as 1 &mgr;m or more, to retain a desirable cell capacitance of the unit cell and solve problems such as low read-out capability of the cell and low immunity to soft error. However, the heights of the three-dimensional capacitors may induce a high global step difference between the cell array area and the peripheral circuit area. The global step difference may make it difficult to form a metal interconnection, which is usually formed after the formation of the capacitors.
One proposal to reduce the global step difference is to form a thick interlayer insulating layer on the global step difference and make the surface of the interlayer insulating layer planar.
FIGS. 1
a
through
1
c
are cross-sectional views illustrating successive process steps for forming a fuse opening according to a conventional method. Referring to
FIG. 1
a
, isolation regions
11
are formed on a semiconductor wafer
10
, thereby defining active regions. MOS transistors
15
are formed on the semiconductor wafer
10
having the isolation regions
11
. Each of the MOS transistors
15
comprises a gate electrode
12
, a source
14
a
and a drain
14
b
. The sources
14
a
and the drains
14
b
are formed in the active regions of the semiconductor wafer
10
. The MOS transistors
15
in a cell array area are formed more densely than the MOS transistors
15
in a peripheral circuit area. Each of the gate electrodes
12
comprises a gate dielectric layer
19
formed on the active regions of the semiconductor wafer
10
, a gate conductive layer
21
formed on the gate dielectric layer
19
, a hard mask layer
25
formed on the gate conductive layer
21
and spacers
27
formed on the sidewalls of the gate conductive layers
21
. Between the gate electrodes
12
, SAC (self-aligned contact) pads
16
are formed to contact the sources
14
a and the drains
14
b.
On the resultant structure, a first interlayer insulating layer
18
is formed. On the first interlayer insulating layer
18
, bit lines (though not shown) and fuse
20
are formed in the cell array area and in the peripheral circuit area, respectively. The bit lines are electrically connected to the drains
14
b
. Though not shown, during formation of the bit line and fuse
20
, a local interconnection may be formed simultaneously on the first interlayer insulating layer
18
in the peripheral circuit area.
On the resultant structure, a second interlayer insulating layer
22
is formed. Subsequently, storage contact holes are formed through the first and second interlayer insulating layers
18
,
22
. The storage contact holes expose the SAC pads
16
, which are formed on the sources
14
a
. Conductive storage contact pads
23
are formed to fill the storage contact holes.
Storage capacitors
30
are formed on the resultant structure. Each of the storage capacitors
30
comprises a concave type storage electrode
24
, a capacitor dielectric layer
26
formed on the storage electrode
24
and a plate electrode
28
formed on the capacitor dielectric layer
26
. The concave type storage electrodes
24
are formed to electrically contact to the storage contact pads
23
. The storage electrodes
24
are formed only in the cell array area, while the plate electrode
28
is formed in both the cell array area and the peripheral circuit area. As a result, as shown in the drawing, a first global step difference X
1
is generated. Though not shown, the plate electrode
28
may be formed only in the cell array area. In this case, the first global step difference XI may be greater compared to that in case of that the plate electrode
28
is formed both in the cell array area and in the peripheral circuit area.
A third interlayer insulating layer
32
is formed on the plate electrode
28
. The third interlayer insulating layer
32
is thick enough to bury the first global step difference X
1
. That is to say, the thickness of the third interlayer insulating layer
32
is greater than the first global step difference X
1
. The third interlayer insulating layer
32
may be formed by a method to make the top surface of the resultant structure planarized to some extent, so that a second global step difference X
1
′ of the resultant structure can be smaller than the first global step difference X
1
. However, it is very difficult to completely remove the second global step difference X
1
′.
Referring to
FIG. 1
b
, a top portion of the third interlayer insulating layer
32
, which is located over the storage electrodes
24
, is removed to reduce the global step difference between the cell array area and the peripheral circuit area. This process is well known in the industry as a cell open process. As a result of the cell open process, a protrusion
34
of the third interlayer insulating layer
32
remains. Preferably, the altitude level of the top surface of the third interlayer insulating layer
32
in the cell array area is adjusted by the cell open process to be substantially the same as that in the peripheral area, thereby substantially removing the global step difference.
Referring to
FIG. 1
c
, the third interlayer insulating layer
32
is subject to a CMP (chemical mechanical polishing) process to remove the protrusion
34
and make the whole surface of the third interlayer insulating layer
32
more perfectly planarized, thereby leaving a planarized interlayer insulating layer
32
a.
Though not shown in the drawings, on the planarized interlayer insulating layer
32
a
, a multilevel metal interconnection including an intermetal insulating layer is formed. A passivation layer (though not shown) is formed on the multilevel metal interconnection. Subsequently, the passivation layer, the intermetal insulating layer, the planarized interlayer insulating layer
32
a
, the plate electrode
28
and the second interlayer insulating layer
22
are selectively etched to form a fuse opening on the fuse
20
, though not shown in the drawings. The reference number ‘
35
’ represents a portion of the planarized interlayer insulating layer
32
a
, which is to be removed to form the fuse opening.
One problem in the above-described method for forming the fuse opening is that the thickness of the planarized interlayer insulating layer
32
a
is too thick in the peripheral circuit area as a result of the process for reducing the global step difference and removing the protrusion
34
. Therefore, the depth of the portion
35
of the planarized insulating layer
32
a
to be etched is too large, resulting in an unfavorably long etching time. The large etching amount and the long etching time may result in low productivity.
Accordingly, the need remains for a method for forming DRAM devices to reduce the etching amount and time for forming a fuse opening, while at the same time significantly reducing the substantial global step difference between a cell array area and a periph

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