Method for forming semiconductor device including stacked dies

Details Method for forming semiconductor device including stacked dies Method for forming semiconductor device including stacked dies

2006-07-04

2006-07-04

Eckert, George (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C257S666000, C257S676000, C228S180210, C228S180220

Reexamination Certificate

active

07071033

ABSTRACT:
A semiconductor device including a leadframe and two stacked dies, a first of which is on a top surface of a leadframe while the second one is on a bottom surface of the leadframe. The drain region of the first die is coupled to a drain clip assembly that includes a drain clip that is in contact with a lead rail. The body of the semiconductor device includes a window or opening that exposes the drain region of the second die.

REFERENCES:
patent: 4514750 (1985-04-01), Adams
patent: 4791473 (1988-12-01), Phy
patent: 5105536 (1992-04-01), Neugebauer et al.
patent: 5233131 (1993-08-01), Liang et al.
patent: 5286679 (1994-02-01), Farnworth et al.
patent: 5512781 (1996-04-01), Inoue
patent: 5544412 (1996-08-01), Romero et al.
patent: 5763952 (1998-06-01), Lynch et al.
patent: 5789803 (1998-08-01), Kinsman
patent: 5986209 (1999-11-01), Tandy
patent: 6040626 (2000-03-01), Cheah et al.
patent: 6066515 (2000-05-01), Schoenfeld
patent: 6081031 (2000-06-01), Letterman, Jr. et al.
patent: 6198163 (2001-03-01), Crowley et al.
patent: 6215176 (2001-04-01), Huang
patent: 6344687 (2002-02-01), Huang et al.
patent: 6373078 (2002-04-01), Yea
patent: 6399418 (2002-06-01), Glenn et al.
patent: 6452278 (2002-09-01), DiCaprio et al.
patent: 6476474 (2002-11-01), Hung
patent: 6661082 (2003-12-01), Granada et al.
patent: 6720642 (2004-04-01), Joshi et al.
patent: 6762067 (2004-07-01), Quinones et al.
patent: 6777786 (2004-08-01), Estacio
patent: 6777800 (2004-08-01), Madrid et al.
patent: 6891256 (2005-05-01), Joshi et al.
patent: 2001/0048116 (2001-12-01), Standing et al.
patent: 2002/0071253 (2002-06-01), Lam et al.
patent: 2002/0086748 (2002-07-01), Pavier
patent: 2003/0025183 (2003-02-01), Thornton et al.
patent: 409116070 (1997-05-01), None
U.S. Appl. No. 09/464,885, Joshi et al., Dec. 16, 1999.
“IR's New Synchronous Rectifier Chip Set Meets New Efficiency Standard for DC—DC Converters to Power Notebook PC Processor Through 2000,” International Rectifier Company Informaton. Retrieved from the World Wide Web at http://www.irf.com/whats-new
r990402.html on Jul. 29, 2003.

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