Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2009-10-08
2011-10-11
Smith, Bradley K (Department: 2894)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S618000, C438S275000, C438S585000, C438S152000, C257SE21575
Reexamination Certificate
active
08034668
ABSTRACT:
A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
REFERENCES:
patent: 6501127 (2002-12-01), Mori
patent: 2005/0179061 (2005-08-01), Jang et al.
patent: 2006/0028861 (2006-02-01), Han et al.
patent: 2000-049351 (2000-02-01), None
patent: 10-2005-0073956 (2005-07-01), None
patent: 10-2006-0012847 (2006-02-01), None
Cho Won-Seok
Jang Jae-Hoon
Jang Young-Chul
Jung Soon-Moon
Son Yang-Soo
Karimy Mohammad T
Lee & Morse P.C.
Samsung Electronics Co,. Ltd.
Smith Bradley K
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