Method for forming self-aligned vias in multi-level metal integr

Details Method for forming self-aligned vias in multi-level metal integr Method for forming self-aligned vias in multi-level metal integr

1989-04-17

1990-04-17

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156652, 156653, 156656, 156657, 1566591, 20419235, 20419237, 437192, C23F 102, B44C 122, C03C 1500, C03C 2506

Patent

active

049177591

ABSTRACT:
A process for forming a via in a semiconductor device using a self-aligned metal pillar to connect metal layers separated by a dielectric. A first aluminum layer is formed on an oxide layer overlying a semiconductor substrate, and a thin tungsten layer is formed and patterned overlying the first aluminum layer. The pattern in this tungsten layer will determine the pattern for the first level of metal interconnect to be formed later in the first aluminum layer. The tungsten layer is etched using the underlying first aluminum layer as an etch stop. A second aluminum layer is then formed overlying the patterned tungsten layer and the exposed regions of the first aluminum layer. In one continuous etching step the second aluminum layer is patterned and etched to form a pillar, and the first aluminum layer is etched to form the first level of metal interconnect in the semiconductor device using the pattern formed earlier in the tungsten layer and to expose regions of the oxide layer. A dielectric is deposited overlying the exposed regions of the oxide layer, the formed pillar, and the thin tungsten layer. This dielectric is etched back to expose the top of the pillar, and then a third aluminum layer is deposited overlying the dielectric to make electrical contact to the exposed surface of the pillar.

REFERENCES:
patent: 4670091 (1987-06-01), Thomas et al.
Reverse Pillar and Maskless Contact-Two Novel Recessed Metal Schemes and Their Comparisons To Conventional VLSI Metallization Schemes, J. L. Yeh et al., I.E.E.E., Jun. 13-14, 1988, V-Mic Conf., pp. 95-100.

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