Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-02-08
2001-02-27
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S233000, C438S595000, C438S647000
Reexamination Certificate
active
06194297
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88100748, filed Jan. 19, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device,, a process for manufacturing such a device, and more particularly, to a process for forming gate spacers.
2. Description of Related Art
In the fabrication of MOS devices on a substrate, the self-aligned silicide (SALICIDE) process is performed to decrease the sheet resistance of the MOS electrodes and the contact resistance of the contact regions between those electrodes.
For decreasing the above mentioned resistances well enough, the salicide process is performed at a high temperature. However, the salicide process cannot be performed as well as required at a temperature of more than about 750° C., especially when the MOS devices comprises a P-type metal oxide semiconductor (PMOS). This is because at such a high temperature, the silicon material in the PMOS gate often oozes out to the spacer adjacent to the gate, and thereby transforms into salicide layers upon the spacer by reacting with the metal layer deposited on the spacer. The salicide layers upon the spacer undesirably, electrically connect the gate with the source/drain regions of the PMOS and often make the PMOS short during operation.
On the other hand, by lowering the temperature to less than about 750° C., it is not easy for other devices, such as an N-type metal oxide semiconductor (NMOS), to form salicide layers upon them, especially when their gate widths are narrowed as the integration of the devices is increased. In addition, the above mentioned resistances cannot be decreased well enough by performing the salicide process at the above temperatures.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating salicide devices. A device pair comprising a first gate structure and a second gate structure is formed on a substrate. The first gate structure comprises a first gate and a stuffed film located on the first gate. The second gate structure comprises a second gate and a stuffed film located on the second gate. A first spacer is formed at the sidewall of the first gate structure, and a second spacer is formed on the sidewall of the second gate structure. The stuffed films are removed, thereby creating a first spacer higher than the first gate. First heavily doped source/drain regions are formed in the substrate adjacent to the first spacer. After the first heavily doped source/drain regions are formed, the first gate and spacer are masked with a photoresist pattern. Second heavily doped source/drain regions are formed in the substrate adjacent to the second spacer. The second spacer is etched back by using the photoresist pattern as an etching mask so as to form a third spacer lower than the second gate. Salicide layers are formed upon the first gate, the second gate, the first heavily doped regions and the second heavily doped regions. The salicide process is performed well at a high temperature of between about 750° C. and 800° C., therefore decreasing the resistance of the MOS electrodes and the contact resistance of the contact regions between those electrodes.
The spacer higher than the first gate prevents the salicide region upon the first gate from laterally growing onto the sidewall of the first gate, especially when the first gate is a PMOS gate.
The spacer lower than the second gate exposes a small, upper part of the sidewall of the second gate so as to leave more sites for forming a gate salicide region thereupon, especially when the second gate is an NMOS gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
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Booth Richard
Gurley Lynne
Huang Jiawei
Patents J C
United Microeletronics Corp.
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