Method for forming programmable interconnect structures and prog

Details Method for forming programmable interconnect structures and prog Method for forming programmable interconnect structures and prog

1997-08-01

1998-07-28

Tsai, Jey

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438131, 438467, 148DIG55, H01L 2144

Patent

active

057862680

ABSTRACT:
Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

REFERENCES:
patent: 4424578 (1984-01-01), Miyamoto
patent: 4441167 (1984-04-01), Principi
patent: 4458297 (1984-07-01), Stopper et al.
patent: 5093711 (1992-03-01), Hirakawa
Actel Corporation, "Antifuse Backgrounder" (Tsantes & Associates, Sunnyvale, CA, Nov. 1991), pp. 1-10.

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