Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-11-30
2004-01-13
Chen, Jack (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S163000, C438S299000, C438S592000, C438S652000
Reexamination Certificate
active
06677189
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a polysilicon thin film transistor (poly-Si TFT) and, more particularly, to a poly-Si TFT with a self-aligned lightly doped drain (LDD) structure.
2. Description of the Related Art
Polysilicon thin film transistors (poly-Si TFTs) are widely used in active matrix liquid crystal display (AMLCD) applications. One of the major problems of these poly-Si TFTs is the OFF-state leakage current, which causes charge loss in LCDs. Seeking to solve this problem, conventional lightly doped drain (LDD) structures have been used to reduce the electric field at the junction of the drain electrode, thereby reducing the leakage current.
FIGS. 1A and 1B
are cross sections showing a conventional method of forming an LDD structure on a poly-Si TFT. As shown in
FIG. 1A
, a polysilicon layer
12
is formed on a predetermined surface of a transparent insulating substrate
10
, and then a gate insulating layer
14
is formed on the polysilicon layer
12
. Next, using a patterned photoresist layer
16
as a mask, a heavy ion implantation process is performed to form an N
+
doped region
18
on the polysilicon layer
12
, and thus the N
+
doped region
18
serves as a source/drain region. As shown in
FIG. 1B
, after removing the patterned photoresist layer
16
, a gate layer
20
is patterned on the gate insulating layer
14
to cover a part of the undoped regions of the polysilicon layer
12
. Next, using the gate layer
20
as a mask, a light ion implantation process is performed to form an N
−
doped region
22
on the undoped region of the polysilicon layer
12
. The N
−
doped region
22
serves as an LDD structure and the polysilicon layer
12
underlying the gate layer
20
serves as a channel.
However, an extra photo mask is required to expose the photoresist layer
16
, and thus an error of alignment, easily caused by the limitation of the exposure technique, may lead to a shift of the LDD structure. This shift of the LDD structure decreases the electrical performance of the poly-Si TFT.
SUMMARY OF THE INVENTION
The present invention provides a poly-Si TFT with a self-aligned LDD structure and a method of forming the same, in which an extra mask is not required to define the pattern of the LDD structure.
The polysilicon thin film transistor with a self-aligned LDD structure has a polysilicon layer formed on a transparent insulating substrate. The polysilicon layer is defined as a channel region, an LDD structure on two sides of the channel region, and a source/drain region on two sides of the LDD structure. A gate insulating layer is formed on the polysilicon layer, a first metal layer is patterned on the gate insulating layer to cover the channel region, and a second metal layer is patterned on the first metal layer to cover the channel region.
The method of forming the polysilicon thin film transistor with the self-aligned LDD structure comprises steps of: (a) providing a transparent insulating substrate with a polysilicon layer formed on the substrate and a gate insulating layer formed on the polysilicon layer; (b) forming a first metal layer, a second metal layer, and a patterned photoresist layer, successively, on the entire surface of the substrate; (c) dry etching to remove the second metal layer and the first metal layer not covered by the patterned photoresist layer; (d) performing a first ion implantation process with the patterned photoresist layer as a mask to form a heavily doped region on the peripheral region of the polysilicon layer; (e) wet etching to remove a part of the peripheral region of the second metal layer so as to expose a part of the peripheral region of the first metal layer; (f) removing the patterned photoresist layer; (g) dry etching to remove the exposed region of the first metal layer so as to level off the sidewalls of the second metal layer and the first metal layer.; and (h) performing a second ion implantation process with the first metal layer and the second metal layer as a mask to form a lightly doped region on the undoped region of the polysilicon layer.
Accordingly, it is a principal object of the invention to provide an undercut structure on the second metal layer to accurately control the position of the LDD structure.
It is another object of the invention to omit an extra photo mask to define the pattern of the LDD structure.
Yet another object of the invention is to prevent the error of alignment easily caused by the limitation of the exposure technique.
It is a further object of the invention to provide the second metal layer to protect the first metal layer.
Still another object of the invention is to provide the second metal layer to reduce resistance.
Another object of the invention is to provide the second metal layer to improve the electrical performance of the poly-Si TFT.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.
REFERENCES:
patent: 6329672 (2001-12-01), Lyu et al.
patent: 2002-94074 (2002-03-01), None
Chen Chih-Chiang
Dai Yuan-Tung
Liao Tsung-Neng
Chen Jack
Industrial Technology Research Institute
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