Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-07-07
2001-01-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S287000, C257S382000
Reexamination Certificate
active
06171939
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a polysilicon gate electrode.
2. Description of Related Art
In the deep submicron regime of semiconductor manufacturing, feature size, contact area, and junction depth are all reduced. To improve the performance of the integrated circuit device and to lower resistance and resistance/capacitance delay, a metal silicide layer is frequently formed as part of a gate electrode in addition to a polysilicon layer. Because the metal silicide layer can be formed without performing a photolithographic operation, the method of forming a silicide layer is often referred to as a self-aligned silicide (Salicide) process. Most salicide layers are formed using titanium silicide (TiSi
x
). Titanium silicide is often used because it has a low resistivity. In addition, a titanium silicide layer can be formed in a controlled manner so that quality and reliability can always be maintained.
However, with the reduction of dimensions of a polysilicon gate electrode, forming a high-quality metal silicide layer above the polysilicon gate electrode is becoming difficult. Growth of the metal silicide layer is stunted by the high level of stress between the metal silicide layer and the polysilicon layer and/or the small number of nucleation sites. Therefore, quality of the silicide layer is likely to deteriorate, sheet resistance of the silicide layer is likely to increase, and performance of the gate electrode will be compromised. For a device whose line width is smaller than 0.18 &mgr;m, quality of the silicide layer is often improved by performing a pre-amorphization implant (PAI) before carrying out the salicide process. The PAI converts a surface layer of the polysilicon into an amorphous silicon layer so that sheet resistance of the subsequently formed salicide layer decreases.
FIGS. 1A through 1C
are schematic, cross-sectional view showing the progression of steps for forming a conventional gate electrode. As shown in
FIG. 1A
, a semiconductor substrate
100
having device isolation structures
102
therein is provided. A gate oxide layer
104
and a doped polysilicon layer
106
are sequentially formed over the substrate
100
. The gate oxide layer
104
and the doped polysilicon layer
106
are patterned to form a gate electrode
108
. To prevent diffusion of light due to surface roughness, an anti-reflection coating
110
, typically made from silicon oxynitride, is formed over the polysilicon layer
106
before the gate oxide layer
104
and the polysilicon layer
106
are patterned. After the polysilicon layer
106
is patterned, hot phosphoric acid is used to remove the anti-reflection coating
110
. However, in the process of removing the anti-reflection coating
110
, a portion of the doped polysilicon layer
106
may be damaged by phosphoric acid. Therefore, a portion of the polysilicon layer in the gate structure may peel off resulting in a degradation of device's performance characteristics.
As shown in
FIG. 1B
, an pre-amorphization implant (PAI) is carried out implanting arsenic ions into the polysilicon gate electrode
108
so that a surface layer of the polysilicon layer
106
is broken down into an amorphous silicon layer
112
. The amorphization of the polysilicon layer
106
facilitates the subsequent formation of a silicide layer. Source/drain regions
114
having a lightly doped drain (LDD) structure is formed in the substrate
100
on each side of the gate electrode
108
.
However, the arsenic (atomic weight=74.9) ions used in the PAI has a relatively high atomic weight. Due to the presence of many large grains inside the polysilicon layer
106
, arsenic ions is able to move along grain boundaries and contact surfaces of the polysilicon layer
106
and the gate oxide layer
104
. Ultimately, the arsenic ions will end up in the channel region of the substrate
100
leading to an intensification of kink effect and the downgrading of device quality.
A layer of titanium (not shown in the figure) is sputtered over the substrate
100
. Using a rapid thermal process, metal in the titanium layer reacts with silicon in the doped polysilicon layer
106
and silicon in the source/drain regions
114
to form a titanium silicide layer
116
. The unreacted titanium is removed by wet etching to form the structure as shown in FIG.
1
C.
In the self-aligned silicide process, some of the dopants within the polysilicon layer
106
will hinder the diffusion of silicon to the titanium layer. The prevention of silicon by dopants is referred to as a dopant effect. Without enough silicon to react with titanium to form a titanium silicide layer, the formation of a high-quality silicide layer is almost impossible.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method for forming polysilicon gate electrode capable of reducing the peeling of polysilicon gate layer due to the removal of anti-reflection coating by phosphoric acid. The method is also capable of moderating kink effect due to penetration of ions in PAI, and dopant effect due to the prevention of silicon diffusion by dopants within the polysilicon gate layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a polysilicon gate electrode. A semiconductor substrate is provided. A gate oxide layer, a partially doped polysilicon layer and an undoped polysilicon layer are sequentially formed over the semiconductor substrate. The undoped polysilicon layer, the partially doped polysilicon layer and the gate oxide layer are patterned to form a gate electrode.
The invention also provides a method for forming a metal-oxide-semiconductor (MOS) transistor. A semiconductor substrate having device isolation structures therein is provided. A gate oxide layer, a partially doped polysilicon layer and an undoped polysilicon layer are sequentially formed over the substrate. The partially doped polysilicon layer and the undoped polysilicon layer are patterned to form a gate electrode. Using the gate electrode as a mask, a lightly doped drain region is formed in the substrate on each side of the gate electrode. Spacers are formed on the sidewalls of the gate electrode. Using the gate electrode and the spacers as a mask, a heavily doped region is formed in the substrate. A metal silicide layer is formed at a top surface of the gate electrode and a top surface of the heavily doped region of the substrate.
An anti-reflection coating can be formed prior to the patterning of the partially doped polysilicon layer and the undoped polysilicon layer. The stacked polysilicon gate electrode of this invention includes an undoped polysilicon layer and a doped polysilicon layer. Since the undoped polysilicon layer is on top to protect the doped polysilicon layer when hot phosphoric acid is used to remove the anti-reflection coating, the doped polysilicon layer is less likely to peel off due to the acid.
In addition, due to the formation of an undoped polysilicon layer above a doped polysilicon layer, dopant effect caused by the presence of dopants inside a doped polysilicon layer in a self-aligned silicide process can be greatly reduced. Hence, quality of the silicide layer will be greatly improved.
Furthermore, the stacked polysilicon gate electrode structure of this invention is able to provide an additional interface. Consequently, when arsenic ions are implanted in a PAI, less arsenic ions will be able to pass through the gate electrode and ends up in the substrate. Without additional arsenic ions in the channel of the substrate, kink effect will be subdued.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5605848 (1997-02-01),
Le Dung A
Nelms David
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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