Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-22
2001-04-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S381000, C257S065000
Reexamination Certificate
active
06211077
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor elements and particularly for forming a polycrystal silicon film on the capacitor electrode surface.
2. Description of the Related Art
Due to the needs for more highly integrated semiconductor devices, further reduction in the cell size is being sought. Particularly in the field of the Dynamic Random Access Memory (DRAM) for which one bit is composed of one transistor and one capacitor, if the cell size is reduced, the electrode area of the capacitor is decreased, hence the capacity value is decreased. As a result, problems such as lowered data hold time and incapability in preventing memory loss caused by an alpha ray will occur.
One method to solve this problem is to use a capacitor with a three-dimensional cylinder structure or a fin structure. However, this method has techincal limitations.
As other methods, there is a method to increase the capacity value by using tantal oxide (Ta
2
O
5
) with a high induction rate or barium strontium titanate (Ba
(x)
Sr
(1−x)
TiO
3
) with a strong induction film. However, this method has not been made fit for practical use.
As another notable method, there is a method called the HSG process that increases the capacity value by making the capacitor surface uneven in order to increase the surface area.
FIG. 1
roughly shows how work progresses in the HSG process. As shown in FIG.
1
(
a
), the amorphous silicon film (
1
) that is the capacitor understructure electrode is formed on the intercalation layer (
3
) formed on the silicon substrate (
8
). The semiconductor substrate (
8
) and the amorphous silicon film (
1
) are linked by polycrystal silicon (
9
). Also, naturally formed oxide film (
2
) adheres to the amorphous silicon film (
1
). After the naturally formed oxide film (
2
) is washed off during pre-processing, the clean surface of the amorphous silicon film (
1
) is exposed. At this point, hydrogen atoms (
5
) are bonded to the dangling bonds on the surface of the amorphous silicon film (
1
) (FIG.
1
(
b
)). This hydrogen (
5
) is desorbed by being heated at a processing temperature of approximately 560° C. and the surface of the amorphous silicon film (
1
) becomes activated (FIG.
1
(
c
)). In an atmosphere of monosilane (SiH4) gas, the mixed-phase active layer of amorphous-polycrystal silicon (
6
) is then selectively formed on the activated surface area by surface reaction (FIG.
1
(
d
)). At this point, if it is annealed at a temperature of approximately 560° C. for a predetermined time period, the mixed-phase active layer amorphous migrates with polycrystal silicon on the surface as a nucleus, crystallizes into polycrystal silicon and the polycrystal silicon grain (
7
) grows. As a result, highly crystalline silicon grains (HSG) (
7
) are formed on the amorphous silicon electrode, resulting in a rough surface (FIG.
1
(
e
)).
Normally, phosphorus (P) is doped on the amorphous silicon electrode surface. For methods for doping phosphorus, there are such methods as Chemical Vapor Deposition (CVD equipment) and Surface-reaction thin film Formation. The former is a method for doping phosphorus at the same time the amorphous silicon film is formed. The latter is a method for selectively growing phosphorus-doped amorphous-polycrystal silicon mixed-phase active layer on the active surface of amorphous silicon.
SUMMARY OF THE INVENTION
The present invention has exploited formation of a rough polysilicon film based on selective migration of amorphous silicon out of an amorphous silicon-polysilicon mixed-phase layer. The present inventors have identified problems and resolved the same as follows:
If using the Surface-reaction thin film Formation Method, as shown in
FIG. 2
, when PH
3
gas of 1% concentration is introduced for the purpose of phosphorus doping during the active state after the heating process (FIG.
2
(
c
)), the phosphorus atom (
10
) of PH
3
gas becomes bonded to a dangling bond (
4
) faster than the silicon atom of SiH
4
gas, and this hinders the growth of the amorphous-polycrystal silicon mixed-phase active layer after that. As a result, an uneven shape is not formed on the surface of the amorphous silicon electrode (
1
) (FIG.
2
(
e
)).
On the other hand, if doping phosphorus using the CVD Method and forming the uneven surface of the amorphous silicon electrode using the HSG Method, a problem that the phosphorus concentration of the HSG surface becomes low occurs due to the lower migration rate of phosphorus (P) than that of silicon (Si). In other words, when a grain in an uneven shape caused by migration is formed, crystallization progresses by amorphous silicon atoms migrating around polycrystal silicon which acts as a nucleus. However, because the migration speed of the phosphorus atom at this point is slower than that of the silicon atom, crystallized silicon atoms make up most of the surface of the grain. As a result, the phosphorus concentration on the HSG surface decreases.
When the phosphorus concentration on the surface decreases and if we measure capacity value by changing voltage, a decrease in the capacitance occurs on negative voltage and the ratio of Cmin/Cmax worsens to 0.95~0.70. which is the ratio of the pre-HSG-formation state. As a result, after expending effort to increase the electrode surface area, the effect of capacity value increase is not obtained sufficiently.
Consequently, an object of an embodiment of the present invention is to provide a method to form an amorphous silicon electrode film with a rough surface made of a polysilicon film (polysilicon grains) by migration of amorphous silicon from an amorphous silicon-polysilicon mixed-phase layer.
Another object of an embodiment of the present invention is to provide a method to form an amorphous silicon electrode film with a rough surface generated by migration, by which the amount of phosphorus doped on the surface does not decrease, a decrease in the ratio of Cmin/Cmax is prevented and the capacitance increases effectively.
In addition, another object of an embodiment of the present invention is to form an amorphous silicon electrode film with a rough surface generated by migration, which film can be mass-produced and which excels in stability and reproducibility.
The present invention includes an aspect to provide a method for forming a rough surface made of a doped polycrystal silicon film on an amorphous silicon film disposed on a semiconductor substrate, comprising the steps of: (a) activating dangling bonds present on a surface of an amorphous silicon film; (b) forming an amorphous silicon-polysilicon mixed-phase layer on the surface of the amorphous silicon film by contacting the dangling bonds with a gas containing silane gas and dopant gas while controlling the ratio of dopant gas to silane gas to bind silicon atoms and dopant atoms to the dangling bonds; and (c) annealing the amorphous silicon-polysilicon mixed-phase layer to form polysilicon grains therefrom, thereby forming a rough surface made of doped polysilicon film.
In the above, the ratio of dopant gas to silane gas can be increased from zero to a predetermined level during formation of the amorphous silicon-polysilicon mixed-phase layer. In the above, the amount of the dopant on the surface can easily be adjusted in a wide range.
In preferable embodiments, the activation of the dangling bonds can be conducted by heating in an inert gas the amorphous silicon film to a temperature of 450° C. to 590° C. The gas may contain various proportions of silane and dopant, e.g., 5% to 60% silane gas and 0.01% to 0.5% dopant gas. Further, the annealing can be conducted at a temperature of 450° C. to 590° C. The annealing can be conducted for 1 minute to 80 minutes until polysilicon grains are formed. The silane may be SiH
4
. and the dopant may be phosphorus (dopant gas may be PH
3
). As silane, disilane, can also be used, and as dopant, PH
3
can also be used.
Another aspect of the present invention provides a method for forming a rough surf
Fukazawa Atsuki
Mori Yukihiro
Shimizu Akira
ASM Japan K.K.
Dang Phuc T.
Knobee Martens Olson & Bear LLP
Nelms David
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