Method for forming polycide gate

Details Method for forming polycide gate Method for forming polycide gate

1999-05-11

2000-08-29

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438655, 438657, 438682, 257412, 257413, H01L 213205, H01L 2144

Patent

active

06110812&

ABSTRACT:
A method for forming a polycide-gate structure is disclosed. The method comprises forming a gate oxide layer on a substrate. Then a polysilicon layer is formed on the gate oxide layer. Next a silicide layer is formed over the polysilicon layer. Thereafter, an amorphous silicon layer is formed on the silicide layer. Then, the amorphous silicon layer, the silicide layer, the polysilicon layer and the gate oxide layer are patterned and etched to define a gate region by using a photoresist mask. Source/drain regions are formed using the gate region as an implant mask. Finally, a cap silicon nitride layer is formed over the amorphous silicon layer.

REFERENCES:
patent: 5441914 (1995-08-01), Taft et al.
patent: 5804499 (1998-09-01), Dehm et al.
patent: 6004869 (1999-12-01), Hu
S. Wolf et al., Silicon Process ing for the VLSI Era, vol. 1, pp. 384-388, 1986.

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