Method for forming patterns for semiconductor devices

Details Method for forming patterns for semiconductor devices Method for forming patterns for semiconductor devices

2001-10-05

2004-07-27

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S678000

Reexamination Certificate

active

06767828

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming patterns for semiconductor devices, and in particular, relates to a method for forming an electrically conductive layer having desired patterns for semiconductor devices
2. Description of the Related Art
Micro-lithography is widely used in various technological fields such as semiconductor devices, display devices, printing devices, etc. Micro-lithography plays an important role especially in the semiconductor manufacturing technology. For instance, photolithography has been used for forming desired patterns in various types of layers for semiconductor devices.
FIG. 1
shows a conventional process for forming desired patterns for semiconductor devices using photolithography. In the conventional process, a layer
101
, such as silicon, silicon nitride, etc., is deposited on a substrate
103
as shown in FIG.
1
(
a
). The substrate
103
is made from, for example, glass, metal, and other suitable materials. A photoresist layer
105
is then formed on the deposited layer
101
as shown in FIG.
1
(
b
). The photoresist layer
105
is typically a positive-type resist or a negative-type resist, and it is typically made from novolak resin combined with diazo ketone compounds, acrylic resin combined with photoinitiators, and polyvinyl phenol combined with onium salts.
The photoresist layer
105
is exposed to a light (e.g., ultraviolet light) in a exposing process as shown in FIG.
1
(
c
). The photoresist layer
105
to be exposed to the light may have a mask with desired patterns. Upon consummation of the exposing process, the photoresist layer
105
is developed by a developer
107
to form patterns
109
on the deposited layer
101
as shown in FIG.
1
(
d
). The developed patterns
109
may be exposed to a post-baking process in FIG.
1
(
e
). Such photolithography technique is well known in this art, thus a detailed description thereof is omitted.
The process further proceeds to an etching process. In the etching process shown in FIG.
1
(
f
), the deposited layer
101
is etched by suitable enchant
111
. The etching process may be carried out in gaseous or liquid atmosphere depending on the enchant
111
. After etching the deposited layer
101
, the patterns
109
(i.e., remaining photoresist) are stripped off using a suitable stripper
113
as shown in FIG.
1
(
g
). Then, as shown in FIG.
1
(
h
), a layer is exposed that is patterned in accordance with the desired patterns in the photoresist layer.
In such conventional process of forming desired patterns on a substrate, many steps are required such as depositing an insulation layer, coating a photoresist layer, exposing the sample to the light, developing the sample with a developing agent, etching the insulation layer, stripping the remaining photoresist layer, etc. Thus, many apparatuses and/or instruments are required to perform the process, and large capital investment is necessary to construct production lines. Furthermore, since the conventional process is typically carried out as a wet process, a great amount of direct and indirect waste material may be produced. As a result, the conventional process requires a high cost in manufacturing semiconductor devices.
Therefore, there is a continuing need for providing a method of forming desired patterns for semiconductor devices which has less processes so as to reduce the product cost and waste material and increase productivity of the semiconductor devices.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming desired patterns for semiconductor devices through a process having reduced steps.
It is another object of the present invention to provide a semiconductor device having a patterned plating layer which is formed through a process having reduced steps.
It is still another object of the present invention to provide a semiconductor metallurgy for forming electrically conductive patterns in a semiconductor device using micro-contact printing and electroless plating processes.
To achieve the above and other objects, the present invention provides a method for forming an electrically conductive layer having predetermined patterns for semiconductor devices. The method includes the steps of providing a substrate, forming on the substrate an insulation layer which has predetermined functional groups, forming a patterned polymer layer having the patterns on the insulation layer, etching the insulation layer in accordance with the patterns of the patterned polymer layer to create a patterned insulation layer, stripping the patterned polymer layer to expose the patterned insulation layer, treating the patterned insulation layer with a coupling agent reacting with the predetermined functional groups, treating the patterned insulation layer with a catalyst-containing solution, and depositing electrically conductive material on the patterned insulation layer.
The insulation layer preferably includes silicon oxides (SiO
x
), and the patterned polymer layer preferably includes solvent soluble polyimide. Preferably, the coupling agent is a silane coupling agent, and the predetermined functional groups are OH functional groups.
By the performing the method of the present invention, a semiconductor device may be provided having a substrate, a patterned insulation layer having predetermined patterns formed on the substrate, and a plating layer formed on the patterned insulation layer, the plating layer having electrically conductive patterns corresponding to the predetermined patterns of the patterned insulation layer, wherein the patterned insulation layer has catalytically active surfaces, and the electrically conductive patterns are formed by depositing electrically conductive material on the catalytically active surfaces of the patterned insulation layer.
In another aspect of the present invention, there is provided a method for forming an electrically conductive layer having patterns for semiconductor devices, including the steps of providing a substrate, forming on the substrate an insulation layer which has predetermined functional groups, forming a patterned polymer layer having the patterns on the insulation layer in which the patterned polymer layer has a coupling agent, etching the insulation layer in accordance with the patterns of the patterned polymer layer to create a patterned insulation layer, stripping the patterned polymer layer to expose the patterned insulation layer, treating the patterned insulation layer with a catalyst-containing solution, and depositing electrically conductive material on the patterned insulation layer.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5079600 (1992-01-01), Schnur et al.
patent: 5851856 (1998-12-01), Nagura
patent: 6348240 (2002-02-01), Calvert et al.

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