Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-06-11
2003-04-29
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S717000, C438S723000
Reexamination Certificate
active
06555479
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to semiconductor fabrication technology, and, more particularly, to techniques for the formation of openings in a process layer for conductive interconnects.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires reducing the size and cross-sectional dimensions of electrical interconnects to active areas, such as N
+
(P
+
) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like. As the size and cross-sectional dimensions of electrical interconnects get smaller, resistance increases and electromigration increases. Aluminum (Al) is frequently used for interconnects in contemporary semiconductor fabrication processes primarily because aluminum is inexpensive and easier to etch than, for example, copper (Cu). However, aluminum has poor electromigration characteristics and higher resistivity than other metals, including copper.
As a result of the difficulty in etching copper, when it is used, an alternative approach to forming vias and metal lines is typically employed. The damascene approach, both single and dual, consisting of etching openings such as trenches in the dielectric for lines and vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25&mgr;) design rule copper-metallized (Cu-metallized) circuits.
In the damascene approach, vias, contact openings and trenches, for example, may be formed in and through dielectric layers and other process layers using known photolithography techniques. A seed layer or film of copper is then formed over the surface of the dielectric and in the openings and trenches. Thereafter, a bulk layer of copper is formed above the wafer using, for example, an electroplating process. The excess copper is then removed by polishing, grinding, and/or etching, such as by chemical/mechanical polishing, to leave only the copper in the openings or trenches, which form the copper interconnects.
One problem associated with the damascene approach arises when both trenches and vias, for example, are formed in the same process layer. Typically, the process requires forming a layer of photoresist material over the process layer and, using well-known photo-lithography techniques, patterning the photoresist layer to allow formation of openings in the dielectric layer for the vias. Thereafter, the openings are etched in the process layer, typically by way of an anisotropic etching process, and the patterned photoresist layer is then removed. A second layer of photoresist material is thereafter formed over the process layer, and this photoresist layer is patterned to allow for formation of the trenches. A second etching process, for example, a second anisotropic etching process, is performed to form the trenches in the process layer, after which the second photoresist layer is removed. Thus, while the damascene approach has numerous advantages, it typically requires additional process steps as compared to more conventional semiconductor manufacturing processes.
The present invention is directed to solving, or at least reducing the effects of, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for forming a patterned process layer. The method comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. The method further comprises performing an anisotropic etching process to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile.
In another aspect of the present invention, a method is provided for forming a patterned process layer. The method comprises forming a process layer above a structure layer, forming a first layer of mask material above the process layer, and forming a second layer of mask material above the first layer of mask material. The method further comprises forming an etch profile in the first and second layers of mask material and performing an anisotropic etching process to form an etched region in the process layer, the etched region having a profile correlating to the etch profile.
In yet another aspect of the present invention, a method is provided for forming a conductive interconnect. The method comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. The method further comprises performing an anisotropic etching process to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile. The method also comprises forming a conductive material in the etched region in the process layer and removing an excess conductive material from above an upper surface of the process layer.
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Wolf et al., Silicon Processing for the VLSI Era, vol. 1, 1986, pp. 182-183.*
Wolf et al., Silicon Processing for the VLSI Era, 1986, vol. 1, p. 407-408.
Beckage Peter J.
Besser Paul R.
Brennan William S.
Hause Frederick N.
Iacoponi John A.
Advanced Micro Devices , Inc.
Deo Duy-Vu
Utech Benjamin L.
Williams Morgan & Amerson P.C.
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