Method for forming multilevel interconnection of semiconductor d

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438641, 438660, 438675, 438688, H01L21/28;21/304

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active

059045574

ABSTRACT:
A method for forming a multilevel interconnection of a semiconductor device of the present invention includes the steps of forming a first wiring layer by depositing a metallic film containing aluminum on an insulating film of a substrate and patterning the metallic film, forming an interlayer insulating film on the entire surface of the substrate to cover the wiring layer from the upper side, forming a connection hole reaching to the first wiring layer at a predetermined position of the interlayer insulating film, selectively depositing aluminum onto an interior of the connection hole at a volume fraction of 100% or more by CVD to fill the interior of the connection hole, flattening the entire upper surface of the interlayer insulating film including the connection hole filled with aluminum by a polishing process, washing the entire surface flattened by the polishing process, and depositing the metallic film containing aluminum at a predetermined position of the upper surface of the flattened and washed interlayer insulating film and patterning the metallic film, thereby forming a second wiring layer connected to the first wiring layer through aluminum filled in the connection hole.

REFERENCES:
patent: 5607718 (1997-03-01), Sasaki et al.
patent: 5627345 (1997-05-01), Yamamoto et al.
patent: 5655954 (1997-08-01), Oishi et al.
Fury, M., "Emerging developments in CMP for semiconductor planarization", Solid State Technology, Apr. 1995, 4 pages.
Krusell, W., et al., "Mechanical brush scrubbing for post-CMP clean", Solid State Technology, Jun. 1995, 4 pages.

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