Method for forming multi-layered metal wiring semiconductor elem

Details Method for forming multi-layered metal wiring semiconductor elem Method for forming multi-layered metal wiring semiconductor elem

1996-07-29

1997-09-02

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438633, 438645, H01L 2128

Patent

active

056631022

ABSTRACT:
A method for forming a Damascene structured multi-layered metal wiring for a semiconductor element, which includes the steps for forming a first insulating layer on the surface of a semiconductor substrate, forming a lower metal wiring pattern on the first insulating layer, forming a second insulating layer on the first insulating layer and the lower metal wiring pattern, forming contacts by subjecting the second insulating layer to etching, successively depositing first and second upper metals over the second insulating layer and the contact, subjecting the second upper metal to etching until the first upper metal is exposed, and forming an upper metal wiring pattern having a double metal structure by subjecting the first upper metal to etching until the second insulating layer is exposed. The upper wiring layer is preferably formed of aluminum deposited by a sputtering method and tungsten deposited by a chemical vapor deposition method.

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patent: 5393703 (1995-02-01), Olowolafe et al.
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