Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-08-24
2004-07-27
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S705000, C438S687000, C134S001200
Reexamination Certificate
active
06767839
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a multi-layer wiring structure, and in particular to applying a so-called damascene method therein.
2. Description of Prior Art
A conventional method for forming the multi-layer wiring or circuit board is shown in FIG.
1
.
In the conventional method, first of all, an aluminum (Al) layer is formed on a substrate, as shown in FIG.
1
(
a
), and on this is provided a resist mask on which patterns are formed. Then, as shown in FIG.
1
(
b
), the aluminum (Al) layer is etched through reactive ion etching (RIE), so as to form lower layer wiring. Next, as shown in FIG.
1
(
c
), applying SOG (spin on glass: applying a liquid obtained by dissolving a silicon compound into an organic solvent, such as alcohol or the like) thereto (although the SOG layer is provided directly on the Al wiring in FIG.
1
(
c
), an insulating film may be provided between the Al wiring and the SOG layer by means of a plasma CVD method), and as shown in FIG.
1
(
d
), the SOG layer is flattened with an etch back. Further, as shown in FIG.
1
(
e
), the SOG is applied on a surface which is flat, and so-called via-holes are formed by etching the SOG layer selectively, as shown in FIG.
1
(
f
). Then, Al is filled into the via-holes, as shown in FIG.
1
(
g
). As shown in FIG.
1
(
g
), an Al film is formed. Furthermore, as shown in FIG.
1
(
h
), the Al film is etched so as to form upper wiring, in the same manner as mentioned above, and the SOG is applied on it to fill up spaces defined among the upper wiring, thereby forming the multi-layer wiring structure.
In actual multi-layer wiring structures, many of them are formed with more than 5 layers by applying the etching technology as mentioned above.
Requirements for high integration of semiconductor devices is increasing more and more, and we are just now entering into a generation of 0.15 &mgr;m in gate length. In this instance, it is already apparent that the characteristics of semiconductor devices can be improved if applying Cu in place of Al, which is conventionally applied, in particular in the following aspects.
Compared with Al, Cu is superior in durability or tolerance against EM (electromigration), and because of a low resistance thereof, it is possible to reduce the delay of signals due to the resistance of the wiring. Also, it is possible to apply a high current density thereto, i.e., it can increase current density allowable to three-times as high as is immediately realized, thereby enabling the minimization of the width of wiring.
However, because it is difficult to control etching rates, in particular on Cu (compared with Al), a copper damascene method receives much attention as a method for realizing the multl-layer wiring of Cu without the etching on Cu.
The explanation of the conventional copper damascene method will refer to FIG.
2
.
First of all, as shown in FIG.
2
(
a
), an insulating film made of either SiO
2
or SOG is formed on a substrate using a CVD method for insulation between layers, and on it is provided a resist mask on which predetermined patterns are formed, so as to form wiring gutters by means of an etching method, as shown in FIG.
2
(
b
). Next, as shown in FIG.
2
(
c
), barrier metal is piled up or accumulated, and then Cu is filled up into the wiring gutters through electroplating or the like so as to form lower layer wiring. as shown in FIG.
2
(
d
). And after polishing the barrier metal and Cu by CMP (chemical polishing), the insulating film for maintaining insulation between layers is formed again on the wiring structure, as shown in FIG.
2
(
e
). In the same manner, hereinafter, by etching the insulating films for insulation between layers, selectively, through the resist mask on which the patterns are formed, via-holes and gutters for upper layer wiring are formed on the insulating films between layers (dual damascene), as shown in FIG.
2
(
f
), and the barrier metal is piled up on those via-holes and gutters for upper layer wiring, as shown in FIG.
2
(
g
). Then, as shown in FIG.
2
(
h
), Cu is filled up into the via-holes and gutters using electroplating or the like, thereby forming the upper layer wiring.
As is mentioned above, in the case of forming the multi-layer wiring (or multi-layer wiring structure) through the copper damascene method, increasing the aspect ratio (height/width) of via-holes comes to be a mandatory factor in minimization. However, in a case where SiO
2
being formed through the CVD is used as the insulating material between the layers, the aspect ratio which can be obtained is 2 at the utmost, which is not satisfactory.
Also, for minimization, a low dielectric constant is necessary for the insulating film between layers; however the dielectric constant of the SiO
2
is ∈=4.1, i.e., it is relatively high.
Application of organic or inorganic SOG having low dielectric constant (∈=3.5 or less than that) has been studied. However, even if the multi-layer wiring is formed using the copper damascene method, applying SOG, the dielectric constant of the SOG comes to be higher, after forming it into the multi-layer wiring than that which the SOG has inherently.
Also, in the case where organic SOG is applied as the material of the insulating film between layers, a defect can easily occur, being called by “poisoned via”.
SUMMARY OF THE INVENTION
The inventors of the present invention acknowledge that, in the case of organic SOG, Si—CH
3
bonding (CH
3
is one example) is cut and changes into Si—OH after forming the multi-layer wiring by using the copper damascene method, for example. While in the case of inorganic SOG, Si—H bonding is cut and changes into Si—OH, and the dielectric constant of the SOG is high due to such changes in structure of the insulating film between layers. Accordingly, the present invention is based on such acknowledgments by the inventors.
Namely, in Japanese Patent Laying-Open No. Hei 8-316228 (1996), for example, there is disclosed a technology, wherein the surface of the inorganic SOG film is densified by treating with an ashing process using O
2
as the main reactant onto the inorganic SOG film under a pressure being equal to or less than 40 Pa, so as to prevent the cutting of the Si—H bonding during heat processing, or processing with organic solvent (which will be taken in steps thereafter), thereby increasing tolerance or durability against moisture absorption.
Then, the present invention is accomplished upon the basis of an assumption that, in the case where the same process is applied to exfoliation (i.e., ashing) of the resist mask obtained by the copper damascene method, the Si—CH
3
bonding will not be cut when the organic SOG is used, and also the Si—H bonding will not be cut when the inorganic SOG is used, thereby enabling the maintenance of the inherent low dielectric constant of SOG.
Namely, according to the present invention, a method of forming a multi-layer wiring structure, comprising the following steps is provided:
etching via-holes or wiring gutters through a resist mask on a silica based insulating film between layers which has a dielectric constant equal to or less than 3.5;
performing an ashing process on said resist mask using oxygen gas plasma under an atmospheric pressure from 0.01 Torr to 30.0 Torr; and
filling up said wiling gutters or said via-holes with conductive material.
Further, preferably, silver, gold, aluminum, copper or the like can be listed as the conductive material mentioned above, and more preferably, copper can be listed. The pressure preferably is within a range from 0.01 Torr to 1.2 Torr. Also, as the method for forming the multi-layer wiring structure a damascene method is preferable, wherein the wiring gutters or the via-holes are filled up with the conductive material after forming barrier metal on the interior surface of the wiring gutters or the via-holes.
The silica based insulating film between layers must have a dielectric constant being equal to or less than 3.5. An organic SOG and
Goudreau George A.
Merchant & Gould P.C.
Tokyo Ohka Kogyo Co. Ltd.
LandOfFree
Method for forming multi-layer wiring structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming multi-layer wiring structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming multi-layer wiring structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3222715