Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-28
2001-11-06
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S623000, C438S666000, C438S667000, C438S672000
Reexamination Certificate
active
06313029
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a multi-layer interconnection of a semiconductor device, and more particularly relates to a method for forming micro-size contact holes for the electrical connection between lower and upper interconnection layers fitted with the fabrication of highly integrated semiconductor devices.
2. Description of the Prior Art
Generally, a semiconductor device is fabricated in the multi-layer interconnection structure. In this multi-layer interconnection structure, a lower interconnection layer and an upper interconnection layer are electrically isolated by an insulating layer having a contact hole, and are electrically connected through the contact hole to each other.
The conventional method for forming the multi-layer interconnection structure will now be described. First, there is provided a semiconductor substrate on which a lower interconnection layer covered by an insulating film is formed. The lower interconnection layer is a metal interconnection or an impurity diffusion region. A contact mask such as a photoresist pattern is then formed on the insulating film. By etching the exposed portion of the insulating film, a contact hole is formed in the insulating film in such a manner that the lower interconnection layer is partially exposed. In the contact hole, there is a contact layer formed in such a manner that it is in contact with the lower interconnection layer. Then, an upper interconnection layer is formed on the insulating film in such a manner that it is in contact with the contact layer.
The contact hole and the contact layer may be formed by a damascene process. In this damascene process, the contact hole is first defined in the insulating layer. A conductive layer is deposited on the insulating film in such a manner that it buries the contact hole. Then, the portion of the conductive layer protruded from the insulating film is removed, thereby forming the contact layer.
In the forming method of the multi-layer interconnection as described above, the contact hole is formed through masking and etching processes. In this case, a realizable size of the contact hole is dependent on a resolution of an exposing system. Namely, the size of the contact hole is limited by an aperture pattern formed on a contact mask, and the size of the aperture pattern formed on the contact mask is dependent on the resolution of the exposing system. For this reason, the realizable size of the contact hole is dependent on the resolution of the exposing system.
A certain size of the contact hole can be realized by the use of an existing exposing system. However, a contact hole having a more reduced size, that is, a micro-size contact hole capable of being fitted with a future tendency toward a high integration density and a design rule reduction, will be not defined, unless a new exposing system is provided.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for forming multi-layer interconnection of semiconductor device, which method allows the formation of a micro-size contact hole fitted with the fabrication of a highly integrated semiconductor device, even by the use of an existing exposing system.
According to an embodiment of the present invention, there is provided a method for forming multi-layer interconnection of semiconductor device, comprising the steps of: providing a semiconductor substrate on which a first interconnection layer is formed; forming a first interlayer insulating film on the first interconnection layer and the semiconductor substrate; forming a patterned etch stopper layer on the first interlayer insulating film such that the etch stopper layer is overlapped with a portion of the first interconnection layer; forming a second interlayer insulating film on the etch stopper layer and the first interlayer insulating film; forming a photoresist pattern on the second interlayer insulating film, in such a manner that a portion of the second interlayer insulating film, which is vertically overlapped with a portion of the first interconnection layer and a portion of the etch stopper layer including the portion overlapped with the first interconnection layer, is exposed; etching the second and first interlayer films using the photoresist pattern and the etch stopper layer such that a contact hole is formed through which the first interconnection layer and a portion of the etch stopper layer are exposed; removing the photoresist pattern; depositing a conductive film at a uniform thickness on the second interlayer insulating film, side walls of the contact hole, the first interconnection layer, and the etch stopper layer; and patterning the conductive film such that a second interconnection layer is formed that is in contact with the first interconnection layer.
According to another embodiment of the present invention, there is provided a method for forming multi-layer interconnection of semiconductor device, comprising the steps of: providing a semiconductor substrate on which a first interconnection layer was formed; forming a interlayer insulating film on the first interconnection layer and the semiconductor substrate; forming a patterned etch stopper layer on the interlayer insulating film such that it is overlapped with a portion of the first interconnection layer; forming a photoresist pattern on the resulting semiconductor substrate, in such a manner that a portion of the interlayer insulating film overlapped with the first interconnection layer, and a portion of the etch stopper layer including the portion overlapped with the first interconnection layer, are exposed; etching the interlayer insulating film using the photoresist pattern and the etch stopper layer such that a contact hole is formed through which the first interconnection layer is exposed; removing the photoresist pattern; depositing a conductive film on the interlayer insulating film and the etch stopper layer such that the contact hole is buried; planarizing the upper surface of the conductive film; and patterning the conductive film such that a second interconnection layer is formed that is in contact with the first interconnection layer.
REFERENCES:
patent: 5726100 (1998-03-01), Givens
patent: 5741741 (1998-04-01), Tseng
patent: 5932928 (1999-08-01), Clampitt
patent: 5985746 (1999-11-01), Kapoor
patent: 6008114 (1999-12-01), Li
patent: 6077769 (2000-06-01), Huang et al.
patent: 6159845 (2000-12-01), Yew et al.
patent: 6171951 (2001-01-01), Lee et al.
patent: 6174804 (2001-01-01), Hsu
patent: 6211063 (2001-04-01), Liu et al.
Hyundai Electronics Industries Co,. Ltd.
Pham Long
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