Method for forming MOS transistors with improved sidewall...

Details Method for forming MOS transistors with improved sidewall... Method for forming MOS transistors with improved sidewall...

2006-07-18

2006-07-18

Everhart, Caridad (Department: 2891)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S723000, C257SE21177

Reexamination Certificate

active

07078347

ABSTRACT:
A gate structure (30) is formed over a semiconductor (10). Sidewall structures (200) of a first width W1are formed adjacent to the gate structure (30) and source and drain regions (90) are formed in the semiconductor (10). An etch process is performed to reduce the width of the sidewall structure to W2and silicide regions (110) are then formed adjacent to the sidewall structures (205).

REFERENCES:
patent: 5460993 (1995-10-01), Hsu et al.
patent: 6190961 (2001-02-01), Lam et al.
patent: 6194279 (2001-02-01), Chen et al.
patent: 6242334 (2001-06-01), Huang et al.
patent: 6455362 (2002-09-01), Tran et al.
patent: 6610571 (2003-08-01), Chen et al.
patent: 2002/0192868 (2002-12-01), Kim

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