Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-04-27
2004-01-27
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000
Reexamination Certificate
active
06682943
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to MRAM semiconductor structures and, in particular, to a method of forming minimally spaced MRAM structures.
BACKGROUND OF THE INVENTION
Magnetic random access memories (MRAMs) employ magnetic multilayer films as storage elements. When in use, an MRAM cell stores information as digital bits, which in turn depend on the alternative states of magnetization of thin magnetic multilayer films forming each memory cell. As such, the MRAM cell has two stable magnetic configurations, high resistance representing a logic state 0 and low resistance representing a logic state 1.
A typical multilayer-film MRAM includes a number of bit or digit lines intersected by a number of word lines. At each intersection, a film of a magnetically coercive material is interposed between the corresponding bit line and digit line. Thus, this magnetic material and the multilayer films from the digit lines form a magnetic memory cell which stores a bit of information.
The basic memory element of an MRAM is a patterned structure of a multilayer material, which is typically composed of a stack of different materials, such as copper (Cu), tantalum (Ta), permalloy (NiFe) or aluminum oxide (Al
2
O
3
), among others. The stack may contain as many as ten different overlapping material layers and the layer sequence may repeat up to ten times. Fabrication of such stacks requires deposition of the thin materials layer by layer, according to a predefined order.
FIG. 1
illustrates an exemplary conventional MRAM structure including MRAM stacks
22
which have three respective associated bit or digit lines
18
. The digit lines
18
, typically formed of copper (Cu), are first formed in an insulating layer
16
formed over underlayers
14
of an integrated circuit (IC) substrate
10
. Underlayers
14
may include, for example, portions of integrated circuitry, such as CMOS circuitry. A pinned layer
20
, typically formed of a ferromagnetic material, is provided over each of the digit lines
18
. A pinned layer is called “pinned” because its magnetization direction does not rotate in the presence of applied magnetic fields.
Conventional digit lines and pinned layers, such as the digit lines
18
and the pinned layers
20
of
FIG. 1
, are typically formed by a damascene process. Although damascene processes are preferred for copper interconnects, in the MRAM cell context the damascene process poses a drawback, in that there is an overlay of the pinned layer
20
with respect to the digit line
18
, which occurs primarily as a result of photoresist misalignment. On
FIG. 1
, this overlay is illustrated by an overlay distance D, on each side of the digit line
18
. Because of technical and processing limitations, conventional damascene processing is unable to produce continuous digit lines and their associated pinned layers.
Another drawback of using conventional damascene process to form the digit lines
18
of an MRAM is the inability of the process to achieve a minimal space or minimum critical dimension CD (
FIG. 1
) between two adjacent digit lines and, consequently, between two adjacent memory cells. Current values of the minimal space or critical dimension are in the range of 0.20 &mgr;m. However, with increased packing density of MRAM cells, the minimal space must decrease to values of 0.1 &mgr;m, or even as low as 0.05 &mgr;m, and current damascene processing does not afford these values with current 248 nm lithography.
Accordingly, there is a need for an improved method for fabricating MRAM structures, such as pinned layers and digit lines, which are minimally spaced from each other, as well as a method for decreasing the critical dimension between two adjacent MRAM structures formed on an integrated circuit substrate.
SUMMARY OF THE INVENTION
The present invention provides a method for forming minimally spaced MRAM structures, such as pinned layers and underlying digit lines, formed over various underlayers of an integrated circuit substrate. The present invention employs a photolithography technique to define a masking pattern followed by a spacer formation on sidewalls of the masking pattern to define minimally spaced digit line regions on an IC substrate, over which MRAM structures are subsequently formed. The space in between the masking patterns is filled with a filler material that has etch selectivity to the masking patterns and spacers. The masking patterns, the lateral spacers, as well as the insulating material below the masking patterns are then etched using the filler material as a hard mask to define minimally spaced etched digit line regions on which MRAM structures are subsequently formed.
These and other features and advantages of the invention will be more apparent from the following detailed description which is provided in connection with the accompanying drawings, which illustrate exemplary embodiments of the invention.
REFERENCES:
patent: 5714039 (1998-02-01), Beilstein, Jr. et al.
patent: 5804458 (1998-09-01), Tehrani et al.
patent: 6174737 (2001-01-01), Durlam et al.
patent: 6555858 (2003-04-01), Jones et al.
Miller, R. J., “High Density, Planar Metal Lands”, IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980, pp. 2270-2276.
Doan Trung T.
Durcan D. Mark
Earl Ren
Keller Dennis
Lee Roger
Dickstein , Shapiro, Morin & Oshinsky, LLP
Tsai Jey
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