Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-01-24
2003-07-01
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S586000, C438S655000, C438S683000, C438S976000
Reexamination Certificate
active
06586321
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a metal silicide layer, and more particularly to a method for forming a cobalt silicide layer or a titanium silicide layer.
2. Description of Related Art
Semiconductor devices have been becoming smaller and smaller in recent years, and this has been accompanied by increases in gate metallization resistance, and in parasitic resistance or contact resistance of the source and drain portions of transistors. Consequently, it has been very difficult to realize the higher speeds that would be anticipated from the scaling rule. A silicide technique, in which a silicide film of a high-melting-point metal is formed in self-aligning fashion over gate and diffusion layer regions, has come to the forefront as a way to solve this problem. This silicide technique affords a decrease in sheet resistance. The use of titanium silicide (TiSi
2
) or cobalt silicide (CoSi
2
) is especially promising from the standpoints of lowering the resistance and achieving thermal stability.
When TiSi
2
is used in a fine device having fine wiring on the order of 0.1 &mgr;m, however, it is necessary during the step of forming the TiSi
2
to effect a phase transformation from high resistance C49 phase TiSi
2
(hereinafter referred to as C49-TiSi
2
) to low resistance C54 phase TiSi
2
(hereinafter referred to as C54-TiSi
2
). With finely patterned C49-TiSi
2
, however, this phase transformation is restricted, which creates a problem called the narrow line effect, in which it is difficult to lower the resistance. If an attempt is made to make the wiring even finer (to less than 0.1 &mgr;m), there is a sharp increase in the sheet resistance of TiSi
2
. This is attributable to the aggregation of the TiSi
2
and the resulting disconnection of the silicide layer.
In contrast, the narrow line effect is not encountered when CoSi
2
is used. Also, in the formation of the CoSi
2
, a cap film made from titanium nitride (TiN) or titanium (Ti) is provided over the top layer of cobalt (Co) provided over the silicon (Si). This allows the oxidation of the surface of the cobalt layer to be suppressed. According to published literature (1993 IEDM Tech. Dig., p. 906), it is possible to lower the resistance of a narrow line pattern of 0.075 &mgr;M CoSi
2
, for example.
Let us at this point refer to
FIGS. 7A-7D
to give a brief description of a common method for using a suicide technique to form a low-resistance CoSi
2
layer over a polysilicon gate electrode and a diffusion layer.
FIGS. 7A-7D
are simplified process diagrams of a conventional low-resistance CoSi
2
layer, and illustrates the steps with cross sections of the structure during formation.
First, a polysilicon gate electrode
102
and diffusion layers
104
that flank this gate electrode
102
on both sides are formed on a silicon substrate
100
by an ordinary method. Isolation regions
106
are on the outsides of the diffusion layers
104
, formed from thick oxide films. Side wall oxide films
108
are formed on the side walls of the gate electrode
102
. Next, a cobalt film
110
is formed by sputtering over the entire main surface of the substrate
100
on which the gate electrode
102
and the diffusion layers
104
have been formed (FIG.
7
(A)). After this, an RTA (Rapid Thermal Annealing) treatment (“first RTA treatment”) is performed at a temperature of 450 to 650° C. The result of this is that the surface of the gate electrode
102
reacts with the portion of the cobalt film
110
in contact with this surface, forming a first CoSi layer
112
(a layer made up of CoSi, CoSi
2
, and a compound of CoSi and CoSi
2
). The surface of the diffusion layers
104
also reacts with the portion of the cobalt film
110
in contact with this surface, forming a second CoSi layer
114
(a layer made up of CoSi, CoSi
2
, and a compound of CoSi and COSi
2
) (FIG.
7
(B)) After this, a sulfuric acid peraqueous solution, a hydrochloric acid peraqueous solution, or the like is used to selectively remove a portion of the unreacted cobalt film
110
(FIG.
7
(C)). A second RTA treatment is then performed at a temperature of 750 to 900° C., which changes the first CoSi layer
112
and the second CoSi layer
114
into first and second CoSi
2
layers
116
and
118
(layers made up almost entirely of CoSi
2
). Thus, a low-resistance first CoSi
2
layer
116
and second CoSi
2
layer
118
can be formed on the surface of the gate electrode
102
and on the diffusion layers
104
(FIG.
7
(D)).
However, the junction depth of a device tends to be shallow as the device becomes more highly integrated. Accordingly, if too much silicon is consumed in the step in which the silicon on the surface of the diffusion layers
104
reacts with the cobalt film
110
to form a CoSi layer, there is the danger that this junction will be broken and leakage current will be generated. It is therefore necessary to reduce the amount of silicon consumption.
One way to reduce the amount of silicon consumption is to form a thinner cobalt film. However, when a cobalt film with a thickness of 10 nm, for example, is formed by sputtering as in the past, the sputtering only lasts about 13 seconds. Therefore, if an attempt is made to make the film even thinner, the film formation time will be shorter still, making it difficult to control the film thickness.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method with which a metal silicide layer with low resistance can be easily formed on a substrate, with minimal consumption of silicon.
In order to achieve this object, the method of the present invention for forming a metal silicide layer comprises the following steps in the formation of a metal silicide layer over a silicon-containing region.
(1-1) A step of forming a first metal layer by depositing a first metal over the silicon-containing region.
(1-2) A step of forming a second metal layer by depositing a second metal over the first metal layer.
(1-3) A step of forming an antioxidation layer over the second metal layer.
(2) A step of performing a first heat treatment on the structure comprising the silicon-containing region, the first metal layer, the second metal layer, and the antioxidation layer (those formed by deposition in steps (1-1) to (1-3)), thereby:
(a) forming a metal silicide preliminary layer from a region on the first metal layer side of the silicon-containing region and a region on the silicon-containing region side of the first metal layer, and
(b) forming an alloy layer including a first metal and a second metal from the second metal layer and a region on the second metal layer side of the first metal layer.
(3) A step of removing the antioxidation layer and then removing the alloy layer and a portion of the remaining first metal layer.
(4) A step of performing a second heat treatment on the metal silicide preliminary layer (the layer formed in step (2)) at a higher temperature than in the first heat treatment so as to change the metal silicide preliminary layer into a metal silicide layer.
With the present invention, the above-mentioned step (2), in which the first heat treatment is performed, involves forming an alloy layer including a first metal and a second metal from the second metal layer and a region on the second metal layer side of the first metal layer, so the metal silicide preliminary layer formed from the region on the first metal layer side of the silicon-containing region and the region on the silicon-containing region side of the first metal layer can be formed in a thickness of only 35 nm or less. This is because part of the first metal layer is consumed in the formation of the alloy layer, so the region of the first metal layer consumed in the formation of the metal silicide preliminary layer is smaller (narrower) than in the past. The above-mentioned step (4), in which the second heat treatment is performed on this metal silicide preliminary layer, makes it possible for a thin-film metal silicide layer to be formed over the silicon-con
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
Wilczewski Mary
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