Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-29
2002-04-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S689000, C438S700000, C438S740000, C438S597000
Reexamination Certificate
active
06380073
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the formation of dual damascene structure, more particularly for forming a metal via structure without corner faceted.
2. Description of the Prior Art
Currently, demand for integrated circuits (I.C.) has rapidly increased due to widespread use of electronic equipment. In particular, the increasing popularity of some electronic equipment such as, for example, many kinds of computers are gradually increasing the demand for the large or very large semiconductor memories. Therefore, the advanced manufacturing technology for improvement fabrication of integrated circuit is in greater demand than before.
Normally, the size and performance of the power IC devices depends critically on a specific point at a particular breakdown voltage of the output devices. Since the thickness of semiconductor is usually limited by technological constraints, higher breakdown voltages typically require more layers. However, since the device on resistance is proportional to the expitaxial layer resistivity, higher breakdown voltages have to generally be traded off for limited drive current capability.
Thus, there is a conventional method described as referring to
FIGS. 1A
to
1
D, which are the method for forming inter-metal dielectric by using dual damascene for precisely controlling the shape and area of the interconnect.
Then, the following description will explain the various steps of one conventional method for forming dual damascene structure by referring to
FIGS. 1A
to
1
E.
In the manufacture of a conventional dual damascene structure, there is a substrate
100
having a stop layer
120
formed therein as shown in FIG.
1
A. An inter-metal dielectric layer
130
and a stop layer
140
are subsequently deposited on the substrate
100
. This stop layer
120
,
140
both are silicon nitride as a trench etching stop layer. Then, the photoresist layer
160
having a via pattern is formed on the stop layer
140
.
Then, an anisotropic etch is performed to etch through the stop layer
140
, and the photoresist layer
160
is removed, as shown in FIG.
1
B.
Referring to
FIG. 1C
, another inter-metal dielectric
150
, another stop layer
170
and another photoresist
161
having the trench pattern are all formed on the surface of stop layer
140
and on the via opening of inter-metal dielectric
130
. The stop layer
140
is used as a mask for the etching process due to the self-alignment via etching for forming the via. Also, the etching selectivity will be higher. If the height of the stop layer
140
is not enough or the etching condition is changed, then the via could be corner faceted. Even the via pattern will be lost.
Then, as shown in
FIG. 1D
, the pattern from the photoresist
161
is transferred by the anisotropy etching. The stop layer
170
, inter-metal dielectric
150
, through the stop layer
140
and the inter-metal dielectric
130
are all etched and stop at the substrate
100
. Then, the photoresist layer
161
is removed. Here, shown as LEGEND
50
, there is an obvious corner faceted established on the via shoulder.
As shown in
FIG. 1E
, a barrier layer
180
is deposited and a metal layer
190
, such as tungsten, aluminum or copper, is subsequently deposited to fill the via hole and trench line. Finally, the dual damascene structure is completed using chemical mechanical polishing to remove excess metal layer.
For 0.18 &mgr;m process and beyond, the dual damascene process is a key technology to push the design rule tightly, but it is difficult to control the process window especially in via and metal trench formation. Thus, good resolution of lithography (a misalignment issue) and high selectivity of via etching is the key issue for back end interconnection.
Therefore, within the microelectronics industry, there is an ongoing trend toward miniaturization coupled with higher performance. The scaling of transistors toward smaller dimensions, higher speeds, and low power has resulted in an urgent need for low constant inter-level insulators. Low dielectric constant inter-level dielectrics have already been identified as being critical to the realization of high performance integrated circuits. Thus, there exists a need in the microelectronics industry for a thermally stable, non-corrosive low dielectric constant polymer with good solvent resistance, high glass transition temperature, good mechanical performance and good adhesive properties, particularly to copper.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming the dual damascene structure that substantially obtains better shape without getting corner faceted.
It is object to fill up a removable dielectric layer into the via profile in order to increase the etching selectivity of the stop layer and the etching selectivity of the dielectric in the via. Thus, the profile can be maintained even if it is under the trench pattern etching.
In one preferred embodiment, a semiconductor substrate is provided, the substrate has a first silicon nitride layer formed thereon, and a first inter-metal layer is formed on the surface of the first stop layer.
A first photoresist layer is formed on the first inter-metal layer, and the first photoresist layer has a metal via pattern formed on. The first inter-metal layer is etched to form an opening in the inter-metal layer using the first photoresist as an etching mask. A second silicon nitride layer is formed on the surface of the first inter-metal layer. A dielectric layer is formed to fill up an opening and the second silicon nitride layer. This above dielectric layer is more removable than the first and the second dielectric layer. Also, the etching selectivity of this dielectric layer to the first, the second and the third silicon nitride layer is higher than the first and second dielectric layer. Then, the dielectric layer is etched back until the second silicon nitride is exposed.
A second inter-metal layer is formed on the surface of the second silicon nitride layer and the dielectric layer. A second photoresist layer is formed on the surface of the second dielectric layer. The second photoresist has a trench opening pattern. The second inter-metal layer is etched using the second photoresist as an etching mask. The third silicon nitride layer is formed on the surface of the second inter-metal layer, the second silicon nitride layer and the dielectric layer. The third silicon nitride layer is etched back until the dielectric layer is exposed. The dielectric layer is removed from the opening. The third silicon nitride layer, the second silicon nitride layer and the first stop layer are etched until the substrate, the first dielectric layer and the second dielectric layer are exposed. The barrier layer is deposited into a via trench which is formed into the first inter-metal layer and the second inter-metal layer. The trenches are filled by a metal layer. Finally, the metal layer is planarized to expose the surface of the second dielectric layer in order to form a metal via structure.
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Hiroi et al. “Dual Hard Mask Process for low-K Porous Organosilica Dielectric in Copper Dual Damascene Interconnect Fabrication”, IEEE 2001, pp. 295-297.
Hung Tsung-Yuan
Hwang Tsing-Fong
Rocchegiani Renzo N.
Smith Matthew
United Microelectronics Corp.
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