Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-06-28
2003-09-23
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S780000, C438S760000
Reexamination Certificate
active
06624092
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for forming an insulating layer with low dielectric constant. More particularly, the present invention relates to a method for forming an insulating layer with foamed structure.
2. Description of Related Art
In order to satisfy the requirement of interconnect after the size of metal-oxide semiconductor transistor is greatly reduced, the interconnect structure designed with multiple metal layers has been the usual way in integrated circuit. Particularly, for a powerful microprocessor, it usually needs four, five, or even more metal layers, so as to accomplish the interconnect structure. This kind of multilevel interconnect needs several insulating layers between for insulating the metal layers, preventing short circuit in the multilevel interconnect.
The spin-on glass (SOG) process is one of conventional methods to form an insulating layer. The SOG process includes a dielectric material which is solved in a solvent as a solution. The solution with dielectric material is coated over a wafer by a pin coating manner, and then the wafer is put on a hot plate for baking, so as to cure the SOG, while the solvent in the solution is evaporated away. After the first stage of curing on the hot plate, the wafer is transferred into a furnace for the final stage of curing.
However, as the size of interconnect is further reduced following fabrication trend, the back-end of line is narrowed, causing a phenomenon of metal line delay. The metal line delay is a severe issue in operation of integrated circuit. This is because when the line width of interconnect is getting narrow, the parasitic capacity is getting more effect and further causing time delay, and even more causing power consumption resulting in raising temperature on the wafer. In this consideration, it is strongly desired that the insulating layer needs smaller dielectric constant.
SUMMARY OF THE INVENTION
The invention provides a method to form an insulating layer with foamed structure, so that the dielectric constant is further reduced. Therefore, it is suitable for use in the more and more complicate device design.
The invention provides a method for forming an insulating layer with a foamed structure. The method uses a subcritical drying process to form the insulating layer with foamed structure. The method includes coating a gel layer over a substrate, where the gel layer includes several types of solution, an unextractable material, and a solvent. A subcritical drying process is performed to extract a to-be-extracted material in the gel layer, so that the gel layer is transformed into the insulating layer with the foamed structure. The foamed structure can reduce the dielectric constant.
Moreover, the subcritical dry mechanism is related to the control between temperature and pressure, so that some extractable materials exited in the polymer gel can be extracted leaving pores, whereby the unextractable material forms a layer with foamed structure, also called porous structure. The temperature and the pressure are set at the critical levels in the three-phase diagram for the extracted material.
Since the invention has employed the subcritical drying process to form the insulating layer with foamed structure, the dielectric constant further lower than that of the conventional low dielectric constant insulating layer. Since the invention uses the subcritical drying process to form the foamed structure, the dimension of each pore un the foamed structure is more uniform. This also allows the electrical transmission between device to be more efficient.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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J.C. Patents
Macronix International Co. Ltd.
Smith Matthew
Yevsikov V.
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