Method for forming landing plug contacts in semiconductor...

Details Method for forming landing plug contacts in semiconductor... Method for forming landing plug contacts in semiconductor...

2007-06-12

2007-06-12

Luu, Chuong Anh (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S256000, C438S279000, C438S399000

Reexamination Certificate

active

10876590

ABSTRACT:
Disclosed is a method for forming landing plug contacts in a semiconductor device. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the gate structures; planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process until the gate hard mask is exposed; forming a hard mask material on the planarized inter-layer insulation layer; patterning the hard mask material, thereby forming a hard mask; forming a plurality of contact holes exposing the substrate disposed between the gate structures by etching the planarized inter-layer insulation layer with use of the hard mask as an etch mask; forming a polysilicon layer on the contact holes; and forming the landing plug contacts buried into the contact holes through a planarization process performed to the polysilicon layer until the gate hard mask is exposed.

REFERENCES:
patent: 5977583 (1999-11-01), Hosotani et al.
patent: 6130449 (2000-10-01), Matsuoka et al.
patent: 6204161 (2001-03-01), Chung et al.
patent: 6435942 (2002-08-01), Jin et al.
patent: 6514821 (2003-02-01), Huang
patent: 2000-08402 (2000-02-01), None
patent: 2001-05107 (2001-01-01), None
patent: 2001-38793 (2001-05-01), None
Notice of Preliminary Rejection from the Korean Patent Office, mailed Aug. 25, 2005, in Patent Application No. 2003-98536, and English translation thereof.

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