Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-04-08
2003-04-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000, C438S296000
Reexamination Certificate
active
06544861
ABSTRACT:
RELATED APPLICATION
This application claims priority from Korean Patent Application No. 2001-18967, filed on Apr. 10, 2001, the contents of which are incorporated herein by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for forming a dent-free isolation trench.
BACKGROUND OF THE INVENTION
A technique for isolating devices formed on a semiconductor substrate has a direct effect on device reliability and basic transistor characteristics. Thus, effective device isolation techniques are important in the development of devices. Inadequate device isolation causes leakage current and results in a loss of a power supplied to a semiconductor chip. Inadequate isolation also increases the occurrence of latch-up and causes temporary or permanent damage to the functions of semiconductor devices. It can also lead to degradation of a noise margin, voltage shift, and/or crosstalk.
In a conventional method for isolating a device region of the semiconductor substrate, a local oxidation of silicon (hereinafter referred to as “LOCOS”) method has been used. In this method, a patterned silicon nitride layer and a pad oxide layer are used to mask a silicon substrate to define an active region therein. The pad oxide layer is used to alleviate a stress caused by the silicon nitride layer. Impurities are implanted into the exposed silicon substrate, and a thick field oxide layer is then locally formed to form a LOCOS structure.
The conventional LOCOS structure has several problems, however, such as so-called “bird's beak encroachment.” Bird's beak encroachment is a lateral extension of the field oxide into the active area of semiconductor devices caused by some of the oxidant diffusing under the edges of the silicon nitride masking layer. Also, during field oxidation, channel stop dopants can laterally diffuse into the active device region, leading to a narrower channel width than desired.
To deal with these problems, a shallow isolation trench is now widely used. In the shallow trench isolation technique, a semiconductor substrate is etched using a trench etch mask to form a trench. The trench is then filled with a chemical vapor deposition (CVD) layer to provide a device isolation layer. Next, the CVD layer is planarized and the trench etch mask is removed.
According to this trench isolation technique, a stress generated by a device isolation material filled in the trench is applied to the sidewalls of the trench, forming a shallow pit therein, or in the active regions. The presence of a pit results in an increase in leakage current in the active device regions and also degrades the insulation characteristics of the isolation trench. The stress can be caused, for example, by a thermal stress generated during depositing or annealing of the CVD layer. A stress can be also caused by the volume expansion resulting from oxygen diffusion during the deposition of the CVD layer.
In order to prevent such stresses, a technique for forming a thermal oxide layer on the sidewalls of a trench and depositing a liner layer of a nitride layer on the thermal oxide layer has been introduced In U.S. Pat. No. 5,447,884 (the '884 patent), for example, a method of forming a nitride liner to provide trench isolation is disclosed. In U.S. Pat. No. 4,631,403, two kinds of oxidation barriers are disclosed—one being a dual layer of oxide-nitride, and the other being a triple layer of oxide-nitride-oxide.
FIGS. 1 and 2
are cross-sectional views of a semiconductor substrate illustrating a conventional method of forming trench isolation using a nitride liner. Referring to
FIG. 1
, a thermal oxide layer
20
is formed on a semiconductor substrate
10
, and a mask nitride layer
14
is formed thereon. These layers are patterned to form a trench etch mask. The semiconductor substrate
10
is etched using the trench etch mask to form a trench therein. A thermal oxidation process is then performed to form a thermal oxide layer in the trench, and a nitride liner
26
is formed on the thermal oxide layer
20
. A trench isolation
20
material
28
is next deposited to fill the trench, and then planarized until the top of the mask nitride layer
14
is exposed.
Referring to
FIG. 2
, an isotropic wet etching process is performed using phosphoric acid on an entire surface of planarized substrate to remove the mask nitride layer
14
. Unfortunately, because the nitride liner
26
is adjacent to the mask nitride layer, a portion of the nitride liner
26
is also etched during this process. In other words, a phosphoric acid solution penetrates into the trench along the nitride liner
26
, and a dent is created in the nitride liner
26
(refer to a circle marked with a dotted line). The size of the dent in the nitride liner
26
increases during subsequent processing steps including a fluoric acid etch process and a cleaning process. This results in large voids being created in the trench. A stringer can be undesirably created in subsequent gate pattern formation steps, forming a bridge between the adjacent storage nodes and degrading the refresh characteristics.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a method for forming an isolation trench is provided to prevent a dent in a nitride liner within the trench.
The method in accordance with an embodiment of the present invention includes forming spacers on the sidewalls of a mask nitride layer and a trench after forming a trench in a semiconductor substrate, and before forming a nitride liner. A thermal oxidation process can be performed after forming the trench and before forming the nitride liner. Preferably, a thermal oxidation process is performed after forming the sidewall spacers and before forming the nitride liner, and at this time, a thermal oxidation process can be further performed after forming the trench.
More specifically, according to an embodiment of the present invention, a trench etch mask pattern including a pad oxide layer
20
and a mask nitride layer is formed on a semiconductor substrate to define an active region. The semiconductor substrate is etched using the mask pattern to form a trench therein. A spacer insulation layer is formed on the resulting structure where the trench is formed. The spacer insulation layer is anisotropically etched to form sidewall spacers on the sidewalls of the mask pattern and the trench. A thermal oxidation process is performed to repair the etch damage resulting from etching the trench and the spacer insulation layer. A nitride liner is formed on the resulting structure where thermal oxidation process is performed. A trench isolation material is formed on the nitride liner to fill the trench. The trench isolation material is planarized until the top of the mask nitride layer is exposed. The mask nitride layer is removed.
In one embodiment, thermal oxidation process can be further performed after forming the trench or after forming the spacer insulation layer.
In another embodiment, the spacer insulation layer is formed of a material having an etch selectivity with respect to the mask nitride layer. It is more preferable that the spacer insulation layer be formed of silicon oxide to a thickness of 50 Å to 1,000 Å by a chemical vapor deposition (CVD) technique.
In yet another embodiment, the etch mask pattern is laterally etched to a width of about 200 Å. Consequently, the distance between the top edge of the trench and the mask nitride layer can increase.
A method for forming an isolation trench is provided according to another embodiment of the present invention. The method includes forming a trench etch mask pattern including a pad oxide layer and a mask nitride layer on a semiconductor substrate to define an active region. Also, the semiconductor substrate is etched using the mask pattern to form a trench therein. The mask pattern is etched in the direction of the active region to a width of about 200 Å. A thermal oxidation process is perfo
Marger & Johnson & McCollom, P.C.
Niebling John F.
Pompey Ron
Samsung Electronics Co,. Ltd.
LandOfFree
Method for forming isolation trench does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming isolation trench, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming isolation trench will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3098873