Method for forming isolation pattern in semiconductor device

Details Method for forming isolation pattern in semiconductor device Method for forming isolation pattern in semiconductor device

2002-12-12

2004-03-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

Reexamination Certificate

active

06706617

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming an isolation pattern in a semiconductor device, and more particularly to a method for forming an isolation pattern in a semiconductor device, which enables a hole-type LPC mask to be employed.
2. Description of the Prior Art
Nowadays, Bluechip devices with a size of 0.16 &mgr;m or less employ isolation (ISO) patterns each having a shape of the letter “I”, that is a linear shape.
In fabricating a Bluechip device, after the linear-shaped isolation patterns are formed, LPC (Landed Plug Contact) patterns are formed in a shape of letter “T” as shown in
FIG. 1
, so as to allow the isolation patterns to be connected to bit lines and short-circuiting between a gate layer and a bit line layer.
In a semiconductor device having the conventional T-shaped LPC patterns as described above, as shown in
FIG. 1
, a plurality of bit lines
13
are arranged at regular intervals in a longitudinal direction, and a plurality of gate lines
11
are arranged at regular intervals in a transverse direction while intersecting the bit lines
13
, on a semiconductor substrate (not shown).
Further, on the semiconductor substrate (not shown), isolation patterns
15
are aligned in a linear form. In this case, the gate lines
11
extend in the vertical direction while crossing over both ends of each of the isolation patterns
15
aligned in a linear shape.
Also, a T-shaped LPC pattern
17
is formed on each of the isolation patterns
15
, and the bit lines
13
extend in the longitudinal direction while crossing over central portions of the LPC patterns
17
.
However, in the conventional method, not only too many times of try and error for simulation but also much time and manpower are necessary, in order to manufacture a perfect mask for the formation of the T-shaped LPC pattern as described above.
Further, the mask has a complicated pattern, which may easily cause errors in the mask. For example, from among various Bluechip devices, the LPC mask shows the worst CD uniformity.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for forming an isolation pattern in a semiconductor device, which enables a hole-type LPC mask to be employed instead of the conventional T-type LPC mask, thereby reducing time and manpower for the manufacture of the mask, since the hole-type LPC mask can be manufactured more easily than the conventional T-type LPC mask.
In order to accomplish this object, there is provided a method for forming an isolation pattern in a semiconductor device, the method comprising the steps of: arranging a plurality of bit lines at regular intervals in a longitudinal direction on a semiconductor substrate; arranging a plurality of gate lines at regular intervals in a transverse direction while intersecting the bit lines; forming isolation patterns on a semiconductor substrate, each of the isolation patterns having wing-like branches in a bent shape, each of the bit lines extending over and overlapping on central portions of the isolation patterns, each of the gate lines being in contact with side end portions of the isolation patterns; and forming first contact holes through the wing-like branches of each of the isolation patterns and forming a second contact hole through the central portion of each of the isolation patterns between the wing-like branches.


REFERENCES:
patent: 5811863 (1998-09-01), Rostoker et al.
patent: 5973376 (1999-10-01), Rostoker et al.
patent: 6020092 (2000-02-01), Sakoh
patent: 6097073 (2000-08-01), Rostoker et al.
patent: 6212980 (2001-04-01), Kratch et al.
patent: 252465 (1990-02-01), None

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