Method for forming interconnects on thin wafers

Details Method for forming interconnects on thin wafers Method for forming interconnects on thin wafers

2005-10-04

2005-10-04

Kebede, Brook (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S613000

Reexamination Certificate

active

06951775

ABSTRACT:
A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.

REFERENCES:
patent: 3458925 (1969-08-01), Napier et al.
patent: 4434434 (1984-02-01), Bhattacharya et al.
patent: 5159535 (1992-10-01), Desai et al.
patent: 5629564 (1997-05-01), Nye, III et al.
patent: 6117299 (2000-09-01), Rinne et al.
patent: 6133136 (2000-10-01), Edelstein et al.
patent: 6219910 (2001-04-01), Murali
patent: 6333559 (2001-12-01), Costrini et al.
patent: 6342434 (2002-01-01), Miyamoto et al.
patent: 6354917 (2002-03-01), Ball
patent: 6528881 (2003-03-01), Tsuboi
patent: 6534387 (2003-03-01), Shinogi et al.
patent: 2000124177 (2000-04-01), None
BUR19980169 Document, Mendelson et al., Method for Mounting Wafer Frame at Backside Grinding (BSG) Tool, Mar. 1999, 3 pages.

Affiliated with

Also associated with

Rating

Method for forming interconnects on thin wafers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming interconnects on thin wafers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming interconnects on thin wafers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3479531