Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-09
2002-05-21
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S299000, C438S669000
Reexamination Certificate
active
06391772
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for forming interconnects in a semiconductor device, more in detail to the method for forming the optimum interconnects in the semiconductor device such as a MOSFET in which charging damages caused by an electron shading effect are suppressed during the formation of the interconnects by etching an interconnect layer deposited on a dielectric layer.
(b) Description of the Related Art
The structure of a semiconductor device such as a MOSFET having a desired interconnect pattern is conventionally prepared by forming an etching mask having the desired interconnect pattern on an interconnect layer deposited on an interlayer dielectric layer and etching the interconnect layer underlying the etching mask by means of a dry-etching process.
For etching the interconnect layer such as an aluminum interconnect layer, a chlorine-based gas such as chlorine (Cl
2
) gas, trichloroboron (BCI
3
) gas or the mixture thereof is used as an etching gas.
When the interconnect layer is etched by using only the chlorine-based gas, the side walls of the interconnect formed by the etching are further etched by the etching gas to make the interconnect thinner This phenomenon is referred to as a side etching. For suppressing the side etching, fluorocarbon-based gas such as CHF
3
and CH
2
F
2
, nitrogen gas or CH
4
/Ar is added to the etching gas. The addition of these gases to the chlorine-based gas forms side-wall films deposited on the side walls of the interconnects by depositing, on the side walls, the polymerized reaction product formed in the gas phase or by the reaction with a photoresist film, and the deposited side-wall films protect the interconnects.
In the dry processes used for fabricating the semiconductor device, especially in the dry-etching process utilizing plasma, problems arise such as charge-up damages caused by charged particles in the plasma.
The main causes of the charge-up damages have been recognized due to the spatial non-uniformity of the plasma. The spatial non-uniformity of the plasma density, the plasma potential and the electron temperature generate the potential between a gate electrode and a substrate to apply an electric stress on the region beneath the gate electrode, thereby arising problems such as the deterioration of the gate oxide film and the increase of the gate leakage current.
When an antenna ratio which is an index defined by a ratio of an area of a metal interconnect to a gate area is large, the influence of the charge-up damages appears more prominent.
The recent improvement of the etching apparatus elevated the regularity of the plasma and considerably suppressed the charging damages due to the plasma non-uniformity.
However, a new charging damage mode referred to as an electron shading damage has been found.
The electron shading damage is described in Jpn. J. Appl. Phys., 32, 6109 (1993) by K. Hashimoto. This publication describes that the electron shading damage depending on the interconnect structure (especially, the aspect ratio) and the electron temperature for controlling the nature of the plasma can be effectively suppressed by reducing the aspect ratio of the interconnect and the electron temperature.
Conventionally, the antenna ratio was not so large, the aspect ratio of the interconnect was not so large and the gate oxide film was thicker. Accordingly, the influence of the charge-up damage was not prominent.
The recent undersize of the semiconductor device provides the thinner gate oxide film and the increased interconnect aspect ratio and antenna ratio.
Conventionally, the electron shading damage is suppressed by increasing the gas pressure for reducing the electron temperature. However, in the finer process, the lower pressure is favorable and the reduction of the electron temperature under the lower pressure is difficult. The reduction of the interconnect aspect ratio is not easy because of the restriction on the circuit design of the semiconductor device. In addition, the relation between the interconnection formation by means of the dry-etching process and the charging damage is not completely elucidated.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a method for forming interconnects in a semiconductor device, which suppresses charging damages based on a clarified causal relation between dry-etching conditions for the interconnects and the charging damages of the semiconductor device, for example, between variation of a threshold voltage of a MOSFET which is an index of the charging damages and the etching conditions.
The present invention provides a method including the steps of: depositing an interconnect layer on an insulator layer overlying a substrate; and etching the interconnect layer by using an etching gas to form a plurality of interconnects extending with a specified line space, said etching step depositing a side-wall film on each side wall of each of said interconnects; said etching step including adjusting an amount of a fluorocarbon-based gas added to said etching gas to control a thickness of said side-wall based on the specified line space, said side-wall film having at least a critical thickness for suppressing etching of the corresponding side wall.
In accordance with the method of the present invention, the damage of the semiconductor device, for example, the damage of a gate electrode and a gate dielectric film of a MOSFET, due to charging imbalance caused by an electron shading effect during the etching of an interconnect layer, can be prevented,
The above and other objects, features and advantages of the present invention will be more apparent from the following description.
REFERENCES:
patent: 11-111677 (1999-04-01), None
Hashimoto, K., “New Phenomena of Charge Damage in Plasma Etching: Heavy Damage Only through Dense-Line Antenna”, Appl. Phys. vol. 32, Part 1, No. 12B, pp. 6109-6113, Dec. 1993.
Soda Eiichi
Tokashiki Ken
Hayes & Soloway P.C.
NEC Corporation
Pham Long
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