Method for forming interconnects for 3-D applications

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S627000, C438S667000, C438S678000, C257SE21586

Reexamination Certificate

active

08003517

ABSTRACT:
A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over a portion of the substrate; (c) removing the second portion of the seed layer; and (d) depositing a metal (215) over the first portion of the seed layer by an electroless process.

REFERENCES:
patent: 6849173 (2005-02-01), Chang et al.
patent: 6852627 (2005-02-01), Sinha et al.
patent: 6908856 (2005-06-01), Beyne et al.
patent: 2004/0242010 (2004-12-01), Deshpande et al.
patent: 2005/0064707 (2005-03-01), Sinha
patent: 2005/0186790 (2005-08-01), Kirby et al.
patent: 2006/0043535 (2006-03-01), Hiatt
patent: 2006/0281215 (2006-12-01), Maruyama et al.
patent: 2007/0082474 (2007-04-01), Shih et al.
patent: 2008/0153265 (2008-06-01), Lyne
Sparks, Terry G. and Jones, Robert E.; “Conductive VIA Formation Utilizing Electroplating”; filed Feb. 27, 2007; U.S. Appl. No. 11/679,512; 17 pages.
Ruythooren, W. et al.; “Via technology for 3D wafer stacking”; IMEC, Belgium 2006; 31 pages.

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