Method for forming interconnections in an integrated circuit

Details Method for forming interconnections in an integrated circuit Method for forming interconnections in an integrated circuit

1997-05-06

1998-12-22

Tsai, Jey

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438783, 438784, H01L 214763

Patent

active

058519190

ABSTRACT:
The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

REFERENCES:
patent: 3553533 (1971-01-01), Haberecht
patent: 4457950 (1984-07-01), Fujita et al.
patent: 5459098 (1995-10-01), Maya
French Search Report from French Patent Application 96 0618, filed May 7, 1996.
French Search Report from French Patent Application 96 06019, filed May 7, 1996.
Solid State Communications, vol. 86, No. 10, 1993, G.B., pp. 619-623, B. Pashmakov, et al., "Photoreduction and Oxidation of Amorphous Indium Oxide".

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