Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-09-15
2001-05-15
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S636000, C438S637000, C438S666000, C438S669000, C438S687000, C438S688000
Reexamination Certificate
active
06232215
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to interconnections formed in integrated circuits having multiple levels of wiring lines.
2. Description of the Related Art
Modem integrated circuits include a high density of devices formed in and on a semiconductor substrate. Connections between devices are formed through conductors in and on the semiconductor substrate as well as through wiring lines formed from layers of metal deposited on insulators over the surface of the semiconductor substrate. For example, an integrated circuit may include connections between diffused regions within the semiconductor substrate and first level and second level metal wiring lines. Such multilevel interconnection schemes rely on the accurate placement of vertically extending conductors between the substrate and the first level wiring lines, between the first level wiring lines and the second level wiring lines, and between the substrate and the second level wiring lines.
FIGS. 1 and 2
illustrate a conventional scheme for forming interconnections between different levels of wiring lines.
FIG. 1
illustrates in partial cross-section an interconnection between a first level wiring line
14
formed on an insulating layer
12
above substrate
10
and a second level wiring line. The first level wiring line
14
may be aluminum or an aluminum alloy and the wiring line
14
typically connects to the substrate at a remote location or to other interconnections or other wiring lines. In the integrated circuit, first level wiring lines
14
are covered by an interlevel insulator
16
, which may be silicon oxide (SiO
2
) formed by chemical vapor deposition (CVD oxide). Vias
18
are formed through the insulator
16
down to the first level wiring lines
14
by conventional photolithography and etching, and then vertically extending metal conductors
20
are formed within the vias to make electrical contact with the first level wiring lines
14
. A second level of wiring is formed by depositing a layer of metal over the surface of the insulator
16
and patterning using conventional photolithography and etching to provide second level wiring lines
22
. The vertically extending conductor
20
connects first level wiring lines
14
to second level wiring lines
22
.
FIG. 2
is a plan view of the interconnection shown in
FIG. 1
, with the cross-section of
FIG. 1
indicated in the
FIG. 2
view by the line extending from
1
to
1
′ in FIG.
2
. As can be seen in the plan view, the interconnection region provided for the first level wiring line
14
includes a contact pad
24
, which is an oversized region larger in width than other portions of the first level wiring line
14
. The larger size of the pad
24
reflects the provision of misalignment tolerances for possible misalignment of the via
18
with respect to the wiring line
14
in the photolithography process. If such an oversized pad region is not provided below the via
18
, then there is an unacceptable possibility that the via will be positioned partially off of the first level wiring line
14
so that the via etch would remove some of the insulation or other material on which the first level wiring line is deposited. Providing such an oversized contact pad is undesirable, however, in that the larger width of a pad
24
prevents wiring lines from being spaced closely.
Still referring to
FIG. 2
, it can also be seen that the diameter of via
18
is typically smaller than the width of the second level wiring line
22
because the second level wiring line
22
must be sufficiently wide to provide misalignment tolerances for possible misalignment of the second level wiring line
22
with respect to the via
18
. Making the second level wiring line wider than the via
18
by a sufficient amount to accommodate possible misalignments is similarly undesirable because the need to provide such misalignment tolerances makes it more difficult to increase the density of integrated circuits.
One conventional strategy adopted in response to this problem is to use tungsten to form the vertically extending conductor
20
shown in FIG.
1
. The via
18
can be filled with tungsten using, for example, the selective deposition of tungsten. The subsequent step of patterning a deposited second metal layer to form second level wiring lines can be performed with much higher accuracy, greatly reducing the size of misalignment tolerances that must be provided, allowing the second level to be narrower than shown in FIG.
2
. Such tungsten plug technology is, however, undesirable because of the expense and the difficulty of the process. In addition, tungsten plug technology still requires the provision of an enlarged contact pad to avoid etching the insulating layer under the first level wiring line that would occur if there were a via misalignment.
Another strategy suggested for improving conventional interconnection techniques is shown in
FIG. 3
, in which structures similar to those shown in
FIGS. 1 and 2
are identified by the same identification numbers. In the
FIG. 3
interconnect, insulating sidewall or spacer structures
26
are formed on either side of the first level wiring line
14
, and no oversize contact pad region is provided. The insulating sidewall structures
26
are typically formed from silicon nitride or a similar material that etches more slowly than either the first insulating layer
12
on which the first level wiring line
14
is formed or the second insulating layer
16
formed over the first wiring line
14
. Accordingly, if there is a misalignment of the mask used for etching the via
18
through the second insulating layer
16
, the insulating layer
12
will not be etched if the misalignment is within the tolerance provided by the width of the insulating sidewall structures
26
. The interconnection illustrated in
FIG. 3
is desirable over the structure illustrated in
FIG. 1
because the misalignment tolerance is provided by the insulating sidewall structures, so that first level metal wiring lines
14
can be spaced more closely without loss of reliability. There is, however, a tendency to produce undesirably resistive lower level wiring lines in the implementation of the
FIG. 3
structure.
SUMMARY OF THE PREFERRED EMBODIMENTS
It is an object of the present invention to provide a system of conductors having different layers of wiring lines connected together through vertical interconnects. In some embodiments of the invention, etch stop structures are provided on either side of lower level wiring lines in the regions where vertical interconnects are to be formed to prevent the etching of underlying insulating regions if there is a misalignment of the interconnect via. A layer of protective material, preferably different from that used to form the etch stop structures, is provided on the surface of the lower level wiring lines to protect the lines from etching in the formation of the interconnect structure. In particularly preferred embodiments of the invention, the combination of the layer of protective material and the sidewall structures protect the lower level wiring lines during at least a portion of the wiring line etching process.
In accordance with a particular aspect of the present invention, a method of producing interconnects for a semiconductor device on a substrate forms a first dielectric layer having a surface and then forms first openings in the first dielectric layer. A first layer of conductive material is deposited over the surface of the first dielectric layer to extend into the first openings. A first layer of protective material is deposited over the first layer of conductive material. A pattern of first interconnect wirings is formed from the first layer of conductive material, the patterned first layer of protective material covering an upper surface of the patterned first layer of conductive material. A first layer of sidewall material is deposited over the patterned first layer of conductive material and then the first layer of sidewall material is etched back to
Bowers Charles
Pham Thanhha
Rabin & Champagne PC
United Microelectronics Corp.
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