Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-08
2001-01-09
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S396000, C438S398000, C438S253000, C438S255000
Reexamination Certificate
active
06171955
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming a hemispherical grained silicon (HSG-Si) structure.
2. Description of the Related Art
Because the integration of integrated circuit increases, it is important for the semiconductor industry to consider new manufacturing techniques that enable fabrication of devices on a sub-micron scale. In a fabrication process of a dynamic random access memory (DRAM), size of a DRAM capacitor needs to be decreased in order to decrease the planar area occupied by the capacitor. However, size reduction decreases the surface area of a bottom electrode of the DRAM capacitor. Hence, the charge-storage capacity of the capacitor is decreased.
One way to increase charge-storage ability of the DRAM capacitor is to use a HSG-Si structure for forming a bottom electrode. An electrode formed with the HSG-Si Structure has a greater surface area, and therefore a greater capacitance for the capacitor is obtained because the HSG-Si structure provides a rough, granular surface.
Current methods for forming the HSG-Si structure include the following steps. A doped amorphous silicon layer is deposited by low-pressure chemical vapor deposition (LPCVD) at 520° C. with SiH
4
serving as a gaseous source. The doped amorphous silicon is deposited to serve as a starting material for HSG silicon growth. A seeding process is performed on the starting material at between 550° C. and 560° C. with a low flow rate (<<40 sccm). The starting material is seeded with silicon hydrides, such as silane (SiH
4
) or disilane (Si
2
H
6
), serving as a gaseous source. The seeded starting material is annealed by a high-vacuumed annealing step to grow the HSG-Si structure at between 550° C. and 590° C.
These conventional method, however, are plagued by several drawbacks, including the following:
1. In the seeding process, a clean surface is an important factor to decide whether or not a wafer is suitable for seeding growth. A contaminated wafer is hard to seed. In order to remove the contaminants from the wafer, an intervening cleaning process with a hydrofluoric acid (HF) must be performed before the seeding process. However, the cleaning process is usually difficult to control. If the cleaning step is not carried out properly, the clean surface provided for seeding growth is decreased. This, in turn, affects the HSG-Si growth. Hence, the surface area of bottom electrode cannot be increased effectively.
2. Another drawback caused by the conventional seeding process is that the step must be carried out in a specific chamber. After performing the seeding process for a period of time, silicon hydrides form on the chamber walls. The thermal conductivity of the chamber is decreased because of the formation of silicon hydrides. The throughput thus is decreased. Therefore, the chamber must be cleaned after a period of time in order to maintain the throughput. However, the chamber-cleaning process often takes six days. This time-consuming cleaning process greatly affects the fabrication process.
3. In the seeding process, only the silicon hydrides are used as seeding materials. A low flow rate (<<40 sccm) is required in order to increase the HSG-Si growth selectivity between the silicon material and the other material. Hence, the seeding process is time-consuming.
SUMMARY OF THE INVENTION
The invention provides a method for forming a hemispherical grained silicon (HSG-Si) structure. An amorphous silicon layer is formed on a substrate. An etching step is performed with an etching solution to etch the amorphous silicon layer. The etching solution comprises a hydrofluoric acid, an oxidizing agent, and H
2
O. A cleaning step is performed with a hydrofluoric solution. An annealing step is performed to form the HSG-Si structure.
So as to obtain a rough surface for forming the HSG-Si structure, the etching step is performed to etch the surface of the amorphous silicon layer to form the cavities. The cavities amplify the degree of roughness of the amorphous silicon layer. Additionally, the contaminates, such as silicon oxide, formed on the amorphous silicon layer are removed during the etching step.
In the invention, the etching step is performed instead of using the conventional seeding step. In contrast with the conventional method, which requires a time-consuming cleaning process to clean the silicon hydrides formed on the wall of the chamber, the duration of the process is effectively reduced by the present invention. Thus, the throughput of the fabricating process according to the present invention is increased.
These and other and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments that are illustrated in the various figures.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Bowers Charles
Huang Jaiwei
J.C. Patents
Smoot Stephen W.
United Semiconductor Corp.
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