Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-07-07
2001-11-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S593000
Reexamination Certificate
active
06316344
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for forming a gate. More particularly, the present invention relates to a method for forming a protective layer to protect a gate during a rapid thermal annealing process.
2. Description of Related Art
Tungsten silicide (WSi
x
) is commonly used as a gate conductor in integrated circuits, especially for memory chips, due to its high thermal stability, low resistivity, low contamination levels and good step coverage. The tungsten silicide layer, which is usually formed by low pressure chemical vapor deposition (LPCVD) with dichlorosilane (SiH
2
Cl
2
) and tungsten hexafluoride (WF
6
) as a gas source, has many advantages—lower fluorine content, improved step coverage, lower post-annealed stress and better adhesion with other materials. Therefore, nowadays, the tungsten silicide layer is formed in the manner described above in some semiconductor processes.
In the process of forming a gate structure, a nitride layer serving as a cap layer of the gate structure is usually formed on a tungsten silicide layer after a doped polysilicon layer and a tungsten silicide layer are formed on a substrate in sequence. The nitride layer is formed by low pressure chemical vapor deposition at about 700-800° C. The LPCVD chamber is a vertical furnace without a load lock, so oxygen contamination can occur during wafer loading.
Since the tungsten silicide layer is in an oxidizing atmosphere at a high temperature, silicon dioxide (SiO
2
) is formed during the process of forming the nitride layer as long as the silicon content of the tungsten silicide layer is adequate. However, if the silicon content of the tungsten silicide layer is limited, an abnormal WSi
x
oxidation effect occurs. Due to the abnormal WSi
x
oxidation effect, WSi
x
is decomposed; thus, SiO
2
, elemental W, WO
2
, WO
3
, and other volatile tungsten oxides are formed. Both WO
2
and WO
3
are volatile (the sublimation point for WO
2
is 800° C.) so that a cracking effect and a blistering effect occur in the tungsten silicide layer.
After the gate structure is defined, a rapid thermal annealing process is performed. The rapid thermal annealing process is usually performed in an oxygen atmosphere and a temperature of the rapid thermal annealing process is raised to about 1000° C., quickly. The rapid thermal annealing process oxidizes sidewalls of the gate structure to form an isolation structure which prevents the gate structure from coupling with a contact or other devices. Oxide protrusions are also easily formed on the sidewalls of the tungsten silicide layer during the rapid thermal annealing process. Therefore, some regions of a subsequently formed spacer are thin or the oxide protrusions protrude from the spacer. In a subsequent process of forming a bit line contact hole, a portion of the gate structure under the thin region of the spacer may be exposed during the etching process. As a result, wordline-to-bitline leakage occurs because the gate structure couples with a plug within the bit line contact hole. If these oxide protrusions protrude from the spacer and block the bit line contact hole, the conductive material does not easily fill the bit line contact hole. So, an open bitline contact problem generates.
Another function of the rapid thermal annealing process is to change the crystal structure and grain size of WSi
x
, so that sheet resistance of the tungsten silicide layer can be reduced. For example, the crystal structure of WSi
x
is transformed into a tetragonal structure by performing the rapid thermal annealing process at 700° C.; the sheet resistance of the tungsten silicide layer is decreased from 30 to 3 ohm/sq. after the rapid thermal annealing process. In addition, the grain size of WSi
x
is less than 100 nm. However, an agglomeration effect of the tungsten silicide layer easily occurs during the rapid thermal annealing process, and hence causes a narrow linewidth effect on the gate structure. Because of the agglomeration effect of the tungsten silicide layer, the surface of the tungsten silicide layer becomes rough, and the sheet resistance of the tungsten silicide layer is increased.
SUMMARY OF THE INVENTION
The invention provides a method for forming a gate. In the method, two protective layers are respectively formed by performing two rapid thermal annealing processes, and the tungsten silicide layer is surrounded by the protective layers. So, degradation mechanisms, the abnormal WSi
x
oxidation effect, the cracking effect, the blistering effect and wordline-to-bitline leakage, are avoided.
The invention provides a method for forming a gate. A gate oxide layer is formed on a substrate having an isolation structure, and a polysilicon layer is formed on the gate oxide layer. A tungsten silicide layer is formed by low pressure chemical vapor deposition with dichlorosilane and tungsten hexafluoride as a gas source on the polysilicon layer. The polysilicon layer and the tungsten silicide layer constitute a polycide layer. A first rapid thermal annealing process is performed in an ammonia atmosphere to form a first protective layer on the tungsten silicide layer. A nitride layer is formed by low pressure chemical vapor deposition on the first protective layer, and then a gate structure is defined. The gate structure comprises the gate oxide layer, the polysilicon layer, the tungsten silicide layer, the first protective layer and the nitride layer. A second rapid thermal annealing process is performed in an ammonia atmosphere to form a second protective layer on sidewalls of the gate oxide layer, the polysilicon layer and the tungsten silicide layer. A spacer is formed and abuts the sidewalls of the first and second protective layers, and the nitride layer.
In the invention, two rapid thermal annealing processes are respectively performed in an ammonia atmosphere, and respectively form protective layers; thus, the tungsten silicide layer is surrounded by protective layers. Because of the protective layer on the tungsten silicide layer, the abnormal WSi
x
oxidation effect that usually occur during the process of forming the nitride layer is avoided, therefore the cracking effect and the blistering effect are also avoided. Wordline-to-bitline leakage and the open bitline contact problem are avoided due to the other protective layer on the sidewalls of the tungsten silicide layer. Furthermore, the rapid thermal annealing processes are performed in an ammonia atmosphere, so the agglomeration effect does not occur. As a result, the sheet resistance of the tungsten silicide layer is reduced and the surface of the tungsten silicide layer is planar. Additionally, the protective layers protect the tungsten silicide layer from chemical attack during cleaning processes. Moreover, the protective layers avoid loss of dopants from the polycide layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5482749 (1996-01-01), Telford et al.
patent: 5483104 (1996-01-01), Godinho et al.
patent: 5756392 (1998-05-01), Lu et al.
patent: 5817562 (1998-10-01), Chang et al.
patent: 5851927 (1998-12-01), Cox et al.
patent: 5920744 (1999-07-01), Wu
patent: 6033978 (2000-03-01), Fujii et al.
patent: 6074908 (2000-06-01), Huang
Lindsay Jr. Walter L.
Niebling John F.
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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