Method for forming gate

Details Method for forming gate Method for forming gate

1998-12-08

2001-08-21

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S655000, C438S711000, C438S714000, C438S592000, C438S303000

Reexamination Certificate

active

06277736

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for forming a gate in a metal oxide semiconductor (MOS) transistor.
2. Description of Related Art
A thin alloy film formed by sputtering deposition is widely used to fabricate electrodes, interconnects, barrier layers and thin film transistors. The materials of the electrode in a MOS transistor comprise, for example, a silicide layer and a polysilicon layer, wherein the silicide layer includes high melting point metals, such as tungsten ails silicide, molybdenum silicide and titanium silicide.
Sputtering deposition includes the following steps. First, the background pressure of the chamber is pumped to a vacuum of about 10
−7
Torr. An inert gas, such as argon (Ar), is introduced into the chamber, and the pressure of the chamber is maintained at about 10
−3
Torr. A metal target disposed at a cathode is bombarded by the argon ions generated by DC discharge and affected by a magnetic field applied to the chamber. The atoms in the surface of the metal target are sputtered and deposited on the substrate to form a metal thin film.
Processes with a critical dimension under 0.25 micron have widely used titanium silicide due to the lower resistivity compared to that of tungsten silicide. Titanium silicide is typically denoted by TiSi
x
, in which X is dependent on the temperature, the pressure and other conditions while forming the alloy. If the X is greater than 2.4. polymer nodules are easily formed to cause some problems in the following step of etching. For example, while using chlorine as an etching gas to define a gate, the etching rate of titanium silicide is fast. On the contrary, the effect of anisotropic etching using chlorine as an etchant is relatively inferior. As a consequence, the sidewall of titanium silicide is over etched to affect the profile of the gate. While chlorine/hexafluoroethane (Cl
2
/C
2
F
6
) is used as the etchant, a better gate profile is obtained, however, since the polymer nodule of titanium silicide is hard to remove, a longer etching time is required.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for forming a gate of a MOS transistor. The gate comprises a titanium silicide layer with a low resistivity. Moreover, by changing the component of an etching gas, the titanium silicide layer is easier etched with a better profile compared to the profile formed by the conventional method.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a gate. A gate oxide layer, a polysilicon layer and a barrier layer are sequentially formed on a substrate, on which an isolation structure is formed. A conductive layer is formed on the barrier layer by sputtering deposition using titanium silicide with a low silicon content as a target. A rapid thermal process (RTP) is performed to remove the polymer nodule formed by sputtering deposition. An anti-reflection layer is formed on the conductive layer. The anti-reflection layer, the conductive layer and the barrier layer are patterned by with an etchant comprising chlorine
itrogen/hexafluoroethane (Cl
2
/N
2
/C
2
F
6
) until the polysilicon layer is exposed. Using the anti-reflection layer, the conductive layer and the barrier layer as a mask, the exposed polysilicon layer and the gate oxide layer underlying the exposed polysilicon layer are removed using an etchant comprising chlorine/hydrogen bromide/helium/oxygen (Cl
2
/HBr/He/O
2
). Etching is performed until the substrate is exposed and a gate is formed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5654570 (1997-08-01), Agnello
patent: 5948703 (1999-09-01), Shen et al.
patent: 5977601 (1999-11-01), Yang et al.
patent: 6015997 (2000-01-01), Hu et al.

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