Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-01-08
2004-12-21
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C430S314000
Reexamination Certificate
active
06833326
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming fine patterns in a semiconductor device using a photolithography process.
2. Description of the Prior Art
As generally known in the art, in the case of a conventional photolithography process in the fabrication of semiconductor devices, a 0.25 &mgr;m design rule has been applied and a KrF light source has been employed. However, the KrF light source has been confronted with limitations in photoresist patterning, and so an ArF light source with 193 nm wavelength substituting for the KrF light source has been tested as to whether it is applicable to the fabrication of semiconductor devices or not.
However, when the ArF light source has been tested in the photolithography process of the fabrication process of semiconductor devices, many problems have occurred, one of which is that the photoresist barrier for the ArF light source must have a high absorption ratio against the 193 nm wavelength in order to improve the etching resistance and thereby reduce the coating thickness of the photoresist.
The ratio of a horizontal thickness of the photoresist against a vertical thickness of the photoresist should be 3:1 in general in order to prevent breakage of the pattern, and the photoresist for the ArF light source has a weak etching resistance half times of an I-line photoresist, so the thinness of the photoresist for the ArF light source becomes a burden on an etching process.
FIGS. 1 and 2
are photographs showing problems produced in the formation of fine patterns in a semiconductor device by using a photoresist for an ArF light source in accordance with the conventional art.
Specifically,
FIG. 1
is a photograph showing results of etching a contact for the formation of a landing plug by using a photoresist for an ArF light source in accordance with the conventional art, and
FIG. 2
is a photograph showing results of etching a gate by using a photoresist for the ArF light source in accordance with the conventional art.
As shown in
FIGS. 1 and 2
, in the case of formation of the contact for forming the landing plug by using the photoresist for the ArF light source having a weak etching resistance, there has occurred a problem in that transformation of the pattern is produced.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for forming fine patterns in a semiconductor device, capable of forming fine patterns by using a photoresist having a good etching resistance.
In order to accomplish this object, there is provided a method for forming a fine pattern in a semiconductor device, comprising the steps of: coating a photoresist layer for an I-line and a positive type ArF photoresist layer on a semiconductor substrate that includes a conductive layer; performing exposure and a first baking process on the resultant substrate by using an etch-mask of a desired pattern to produce alcohol radicals (OH
−
) or carboxyl acid (COOH) in the positive type ArF photoresist layer, in which a silylation reaction can occur; removing the etch-mask; performing a development process to the resultant structure to form a first photoresist pattern; performing exposure and a second baking process on the substrate including the first photoresist pattern; performing a silylation process to the substrate to which the second baking process has been performed, by using a HMDS to form a silicon oxide layer on the surface of the first photoresist pattern through reaction between the alcohol radicals (OH
−
) or the carboxyl acid (COOH) and the HMDS; performing a dry development process to the photoresist layer for the I-line by using the first photoresist pattern together with the silicon oxide layer as an etch-mask in order to form a second photoresist pattern; and etching the conductive layer by using the first and second photoresist patterns along with the silicon oxide layer as an etch-mask in order to form bit-lines.
In the embodiment of the present invention, the substrate is vapor treated, prior to the coating of the photoresist layer for the I-line.
Also, photoresist layer for the I-line is coated to the thickness of 0.2 to 1.5 &mgr;m, and the positive type ArF photoresist layer is coated to the thickness of 0.05 to 0.2 &mgr;m.
Further, a step of performing a hard baking process to the photoresist layer for the I-line for 90 seconds at the temperature of 200° C. is added, prior to the coating of the positive type ArF photoresist layer, and a step of performing a soft baking for 90 seconds at the temperature of 110° C. can be added after the coating of the positive type ArF photoresist layer.
In the present invention, the development process is performed for 60 seconds by using a TMAH solution, and the concentration of the TMAH solution is 0.1 to 10%.
Also, the ArF exposure process is performed with supplying energy of 5 to 50 mJ/cm
2
in the step of performing exposure and second baking process to the substrate including the first photoresist pattern.
In the present invention, the first and second baking processes are performed for 90 seconds at the temperature of 110° C., and the silylation process is performed for 90 seconds at the temperature of 120° C.
Further, the silyalating agent used in the silylation process is any one compound selected from the group composed of hexamethyl disilazane, tetramethyl disilazane, bisdimethylamino dimethylsilane, bisdimethylamino methylsilane, dimethylsilyl dimethylamine, dimethylsilyl diethylamine, trimethylsilyl dimethylamine, trimethylsilyl diethylamine, and dimethylamino pentamethyldisilane.
In the present invention, the dry development process is performed using an oxygen plasma, and is performed with maintaining an upper electrode at 500 watts (W) and a lower electrode at 100 watts (W), and applying a bias power of 75 watts (W) and supplying oxygen gas of 35 sccm at the temperature of 30° C. and the pressure of 5 mTorr.
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Hyun Yoon Suk
Koh Cha Won
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Pham Long
Trinh (Vikki) Hoa B.
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