Method for forming fine pattern by spacer patterning technology

Details Method for forming fine pattern by spacer patterning technology Method for forming fine pattern by spacer patterning technology

2008-06-30

2010-06-01

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257SE21240

Reexamination Certificate

active

07727889

ABSTRACT:
In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer is attached to a sidewall of the partition. Thereafter, the spacer is divided into bar patterns by selectively removing the partition. A polysilicon layer pattern is formed by selectively etching a portion of the poly silicon layer exposed by the divided bar patterns and then a target layer pattern is formed by selectively etching a portion of the target layer exposed by the polysilicon layer pattern.

REFERENCES:
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patent: 2004/0142251 (2004-07-01), Hsu et al.
patent: 2006/0134909 (2006-06-01), Nagase et al.
patent: 2006/0240361 (2006-10-01), Lee et al.
patent: 2007/0212892 (2007-09-01), Caspary et al.
patent: 2007/0249170 (2007-10-01), Kewley
patent: 2009/0154214 (2009-06-01), Sugimae et al.

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