Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-19
2002-06-11
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S401000, C438S675000
Reexamination Certificate
active
06403468
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for forming an embedded metal wiring, more in detail to the method for forming the embedding metal wiring having reduced structural defects such as a dishing and a recess.
(b) Description of the Related Art
With the demand of miniaturization and high integration of semiconductor devices, wirings of the semiconductor device are also made thinner and multi-layered. In a method of forming a wiring layer on a dielectric film and of patterning the layer to make a wiring, deficiencies such as snapping and short-circuit failures are likely to be generated in the wiring.
In place of the method of forming the wiring on the dielectric film, a so-called Damisin process is practiced which forms an embedded metal wiring in the dielectric film.
A conventional method of forming an embedded metal wiring will be described referring to
FIGS. 1A
to
1
E.
As shown in
FIG. 1A
, a photoresist film
13
is formed
11
.
Then, as shown in
FIG. 1B
, an etching mask
13
A having a desired wiring pattern is formed by patterning the photoresist film
13
. By employing the etching mask
13
A, the SiO
2
film
12
is etched to form a wiring trench
14
.
After the etching mask
13
A is removed, a barrier metal film
15
is formed on the SiO
2
film
12
including on the wall and the bottom of the wiring trench
14
as shown in FIG.
1
C. The barrier metal layer
15
prevents diffusion of Cu in the silicon substrate
11
and elevates adhesion between the Cu and the SiO
2
film
12
. Examples of the metal employed in the barrier metal film
15
include a high melting point metal such as Ti, Ta and W and a high melting metal nitride such as TiN, TaN and WN.
A conductive metal film
16
, for example, a Cu film is further formed on the barrier metal film
15
as shown in FIG.
1
D.
An embedded wiring Cu
17
including the barrier metal film
15
and the Cu film
16
and embedded in the wiring trench
14
is left in the trench
14
after polishing the Cu film
16
and then the barrier metal film
15
for removal by means of CMP processing which employs a polishing apparatus
20
. In place of the SiO
2
film
11
, a three-layered structure including a lower SiO
2
film, an etching stopper layer and an upper SiO
2
film may be formed to make an etching stopper for etching the wiring trench
14
.
The CMP processing is conducted by employing a polishing apparatus, for example, as shown in FIG.
2
.
The polishing apparatus
20
includes a polishing board
26
rotating around a rotational axis
24
and having a polishing pad
22
thereon, a wafer holder
30
rotating around a rotational axis
28
and supporting a wafer W to be polished on its bottom surface, and a polishing agent nozzle
32
for supplying a polishing agent
36
supplied from a polishing agent supplying system
34
onto the polishing pad
22
as shown in FIG.
2
.
The polishing board
26
and the wafer holder
30
are driven by a driving apparatus (not shown) such as an electric motor. The wafer holder
30
includes a zipping mechanism for zipping the wafer W such as a vacuum absorption mechanism and a mechanical zipping mechanism on its bottom surface, and holding the wafer W.
A slurry-like polishing liquid including polishing particles such as alumina and silica added with an oxidizing agent such as hydrogen peroxide is used as the polishing agent.
When the CMP processing is performed, the polishing pad
22
is mounted on the polishing board
26
and the polishing agent is dropped onto the polishing pad
26
from the polishing agent nozzle
32
while the polishing pad
26
is rotated. On the other hand, the wafer W which is held on the bottom surface of the wafer holder
30
is rotated while it is pressed against the polishing pad
22
.
Thereby, the bottom surface of the wafer W is polished by a desired thickness by means of a cooperative function between the polishing agent and the polishing pad
22
.
However, in the above-mentioned conventional method for forming the embedded metal wiring, formation of the Cu wiring having a desired shape is difficult when the Cu wiring including the barrier metal film and the Cu film in the wiring trench is formed by polishing the Cu film and then the exposed barrier metal film.
When the width of the wiring is large, the central part thereof in the wiring trench is excessively polished to provide a concave or a so-called dishing as shown in FIG.
3
A. When the width of the wiring is small, the Cu film
16
thereof in the wiring trench is entirely and excessively polished to provide a recess as shown in FIG.
3
B.
Because of these reasons, the resistance of the Cu wiring
16
may be increased significantly compared to a design value by reflecting a reduced cross-sectional area of the wiring depending on a degree of polishing.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a method for forming an embedded metal wiring with reduced structural defects such as a dishing and a recess by adjusting concentrations of oxidizing agents to be employed.
The present invention provides a method for forming an embedded metal wiring comprising the steps of patterning a dielectric film overlying a semiconductor substrate to form a wiring trench having a first depth; forming a barrier metal film on said dielectric film, said barrier metal film having a thickness smaller than said first depth; forming a conductive metal film on said barrier metal film while filling said wiring trench with said conductive metal; polishing said conductive metal film by use of a polishing liquid and an oxidizing agent having a first concentration with respect to said polishing liquid to expose said barrier metal film on a region other than said wiring trench; and polishing said exposed barrier metal film by use of a polishing liquid and an oxidizing agent having a second concentration with respect to said polishing liquid lower than said first concentration to leave said barrier metal film and said conductive metal film in said wiring trench.
In accordance with the method for forming the embedded metal wiring of the present invention, the metal wiring having a sectional shape with reduced structural defects such as a dishing and a recess can be formed by employing one polishing apparatus by means of lowering a function of being polished of the conductive metal film embedded in the wiring trench, which is achieved by employing the polishing agent having the oxidizing agent of quite a low concentration when the exposed barrier metal film on the region other than the wiring trench is polished and removed.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.
REFERENCES:
patent: 6114215 (2000-10-01), Osugi et al.
patent: 6136693 (2000-10-01), Chan et al.
patent: 7-58201 (1995-09-01), None
patent: H9-55363 (1997-02-01), None
patent: H9-167768 (1997-06-01), None
patent: H10-135163 (1998-05-01), None
patent: H10-214834 (1998-08-01), None
Christianson Keith
Hayes & Soloway P.C.
Huynh Yennhu B.
NEC Corporation
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