Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1998-12-10
2001-05-15
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S766000, C438S966000, C257S638000
Reexamination Certificate
active
06232206
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to a method for selective oxidation on source/drain regions of transistors of an integrated circuit.
BACKGROUND OF THE INVENTION
In the manufacturing process of the integrated circuit, it is important to form a thin silicide layer on the source/drain regions of the transistors in order to reduce the resistance of the source/drain regions for maintaining high performance of the transistor and resultant circuits. The silicidation on the source/drain regions can be achieved by a simple silicidation on the source/drain regions alone or by the self-aligned silicidation on the source/drain regions and the gate regions of the transistors. It has been well known that the electrostatic discharge (ESD) robustness is a critical parameter of the product of the resultant circuits. However, it is severely impaired by the silicidation. Therefore, several methods have been developed to prevent the electrostatic discharge protection of the transistor from getting worsen due to the silicidation. One method is to utilize the selective implantation of phosphorus ion or arsenic ion into the source/drain regions of the transistors for allowing the growth of a thicker oxide and preventing the silicidation on the source/drain regions. However, phosphorus ion and arsenic ion, both of which are active dopants to silicon, will significantly affect the drain engineering structure of ESD transistor that is not compatible with the design for the deep sub-micron device. Furthermore, this kind of method is only suitable for avoiding the silicidation on n-channel ESD transistors, but not simultaneously on n-channel and p-channel ESD transistors. It is the purpose of the present invention to deal with the above situation encountered by the prior art.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for selective oxidation on source/drain regions of transistors on an integrated circuit.
According to the present invention, the method includes the steps of a) incorporating a neutral species into the first kind of source/drain regions, and b) forming oxidation regions over the first kind of source/drain regions and second kind of source/drain regions, wherein the oxidation regions over the second kind are thicker than the oxidation regions over the first kind.
In accordance with one aspect of the present invention, the neutral species is incorporated into the first kind of source/drain regions by ion implantation. Preferably, the neutral species is nitrogen. Nitrogen is implanted into the first kind of source/drain regions and an annealing process is performed at 900° C. for 20 seconds in the presence of nitrogen. The concentration of the neutral species implanted into the first kind of source/drain regions is about 1×10
15
cm
−2
.
In accordance with another aspect of the present invention, each of the oxidation regions over the second kind of source/drain regions has a thickness of more than 50 Å and each of the oxidation regions over the first kind has a thickness ranged from 10 Å to 15 Å.
In accordance with another aspect of the present invention, the step (b) is performed by thermal oxidation, preferably under the condition of 900° C., 500 torr for 120 seconds.
After the step (b), the method further includes the steps of c) forming a metal layer over the first and second kinds of the source/drain regions and d) performing a salicidation to form silicide regions on the first kind. In addition, the method further includes a step after the step (d) to remove the unreacted metal layer on the second kind.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:
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patent: 5413969 (1995-05-01), Huang
patent: 5908313 (1999-06-01), Chau et al.
patent: 5933721 (1999-08-01), Hause et al.
patent: 6022769 (2000-02-01), Wu
patent: 6033998 (2000-03-01), Aronowitz et al.
patent: 6114257 (2000-09-01), Ronsheim
T. Kuroi et al., Novel NICE (Nitrogen Implantation into CMOS Gate Electrode and Source/Drain) Structure for Hig Performance 0.25um Dual Gate CMOS, IDEM Dec. 1993, pp. 325-328.*
(1) Doyle et al., Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing (1995) IEEE Electron Device Letters, vol. 16, No. 7, p. 301-302.
Huang Tiao-Yuan
Lin Horng-Chih
Coleman William David
National Science Council
Pham Long
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