Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-06-11
2004-07-27
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06767827
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor processing, and more particularly to a method and process for dual inlaid structures for integrated circuit interconnections.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) are formed on semiconductor substrates using a number of different processing steps to create transistor and interconnection elements. In order to electrically connect transistor terminals associated with the semiconductor substrate, conductive (e.g., metal) vias (vertical channels) and interconnections (interconnects) are formed in dielectric (electrically insulating) materials as part of the integrated circuit. The vias and interconnects couple electrical signals and power between transistors, internal circuits of the IC, and circuits external to the IC.
Dual inlaid (“damascene”) interconnect processes for semiconductor devices are replacing conventional blanket metal deposition and etch processes. Traditionally, metal films have been deposited and patterned using photolithography techniques to form patterned metal interconnects overlying a semiconductor substrate. As interconnect geometry sizes decrease and as conductive lines are formed closer together, it becomes increasingly difficult to accurately pattern the conductive lines and form the conductive interconnects using the traditional blanket deposition and patterning processes. Consequently, inlaid metal interconnect processes have been developed to overcome some of these problems.
An example of a conventional self-aligned dual damascene process is depicted in prior art
FIGS. 1A-1E
.
FIG. 1A
shows an etch stop layer (“ESL”)
13
, such as silicon nitride, that is deposited over an existing interconnect pattern formed in an interconnect layer
10
. The interconnect layer
10
may include a patterned conductive material
12
, such as copper. A layer of low-k dielectric material
16
is then deposited on the bottom ESL
13
. A middle stop layer (“MSL”)
18
, such as silicon dioxide or SiN, is deposited over the low-k dielectric material
16
. A via pattern
19
is then etched into the MSL
18
using conventional photolithography and etching techniques, as illustrated in FIG.
1
A.
A second layer of low-k dielectric material
22
is deposited or spin-coated on the MSL
18
and the opening
19
formed in the MSL
18
. A cap, or hard mask layer
24
, such as silicon dioxide or SiON, is then deposited on the dielectric layer
22
, as illustrated in prior art FIG.
1
B.
A trench and via pattern is then formed using conventional photolithography techniques, for example, with a photoresist and an anisotropic dry etch. A first anisotropic dry etch etches through cap layer
24
, followed by a second anisotropic dry etch
25
that etches through dielectric layers
22
and
16
but not the cap layer
24
, MSL
18
or ESL
13
. The second etch
25
results in the formation of a trench
26
and a via
28
, as illustrated in prior art FIG.
1
C.
In prior art
FIG. 1D
the exposed portion of the ESL
13
is then removed by a different etch, etch
27
, to expose the conductor
12
so that the conductor may connect to overlying conductive lines through the trench
26
through the via
28
, respectively.
Following formation of the trenches and vias, a conductive material
30
may be deposited through any of numerous conventional means into the opening and polished back by CMP to level
32
. Cap layer
24
serves as a stop layer during CMP, as illustrated in prior art FIG.
1
E.
Removing the ESL layer
13
from the trenches
26
and the vias
28
prior to filling them with conductive material creates several deleterious effects. In particular, when the ESL layer
13
is etched from the via
28
, the cap layer
24
and the MSL
18
are also etched to some degree, causing the corners of the cap layer and MSL to become rounded near the trenches
26
and vias
28
. The cap
24
and the MSL
18
must therefore be thick enough to survive the ESL etch and protect the underlying ILD layers
16
and
22
. Utilizing thick cap and middle layers, however, comes at the expense of the dielectric constant of the “stack” (i.e., the layers of the ESL, ILDs, MSL, and cap). Because the thickness of the cap
24
and the MSL
18
depend, in part, on surviving the ESL etch, the layers are not necessarily optimized to have the lowest dielectric stack constant. Further, non-uniform ESL etching from feature loading effects may lead to poorly defined trench heights.
In addition, corner rounding induced during the via definition of the MSL
18
, as illustrated in
FIG. 1A
, may further complicate the final profile and require additional thickness increases in the MSL
18
to insure that the corners can survive the subsequent etches. Increased thickness of the MSL
18
, however, undesirably leads to a higher dielectric constant of the stack.
An additional complication that needs to be considered is the transition from relatively thick 248 nm photoresists to thinned 248 nm photoresists, 193 nm photoresists, and even bi-layer or tri-layer photoresists. Each of these changes can lead to complications since robustness to the etch process is significantly different in each of these scenarios.
Additionally, after the trenches
26
and vias
28
are filled with the conductive material
30
, a top surface
32
thereof must be polished back to the hard cap layer
24
in order to remove the metal from the surface and isolate the interconnect patterns. The corner rounding of the cap layer
24
may require additional polishing of the conductive layer
30
to isolate the interconnect patterns, and such additional polishing may damage the underlying ILD layer
22
. As interconnect patterns become more dense, corner rounding of the cap layer
24
leads to increasingly thick cap layers or dual layers to compensate for the additional polishing needed to isolate the interconnect features.
Further, the ESL etch can cause ILD attack and modification due to the etchant contacting the sidewalls of the ILD trenches
26
and vias
28
. This attack on the ILD layer sidewalls may lead to a higher dielectric constant of the stack and decreased performance of the interconnect patterns. Also, under-layer sputtering of copper (when copper is employed as the underlying conductive structure
12
) on the ILD layer sidewalls may increase electromigration and leakage of copper within the structure.
A further problem of conventional dual inlaid metal interconnect processing is feature dependent loading effects during the etch process. Further, certain areas, such as near the die seal or lithography alignment marks, can etch significantly faster than other areas of the die. This difference in etch rate can lead to punch through of the ESL
13
in the fast etching areas. Further, these fast etching areas can have charge build-up which can result in conductor charging and explosion.
Therefore, a method and process for dual inlaid processing is desired that allows for optimal thickness of the cap and MSL materials to improve the dielectric constant of the stack, requiring less polishing to isolate features (e.g. less corner rounding), and allows for the use of single layer photoresists. It is also desired to provide a method that minimizes ILD attack and modification, and prevents underlying sputtering on the ILD sidewalls to improve the dielectric constant and electromigration performance of the stack. Further, it is desired to optimize the ESL for electromigration performance, decreased dielectric constant, and prevent possible punch through of the ESL layer during the ESL etch.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is pre
Kai James
Okada Lynne A.
Wang Fei
Advanced Micro Devices , Inc.
Harrison Monica D.
Pert Evan
LandOfFree
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