Method for forming dual damascenes

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S709000, C438S740000, C438S947000, C438S976000

Reexamination Certificate

active

06946391

ABSTRACT:
A method for forming a dual damascene structure in a semiconductor device manufacturing process including providing a process wafer including a via opening extending through at least one dielectric insulating layer; blanket depositing a negative photoresist layer to include filling the via opening; blanket depositing a positive photoresist layer over and contacting the negative photoresist layer; photolithographically patterning the positive photoresist layer to form a trench opening etching pattern overlying and encompassing the via opening; etching back the negative photoresist layer to form a via plug having a predetermined thickness; and, etching a trench opening according to the trench opening etching pattern.

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patent: 2004/0121578 (2004-06-01), Nam
patent: 2002-0083525 (2002-12-01), None
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patent: 400620 (2000-08-01), None
patent: 471125 (2002-08-01), None

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