Method for forming dual damascene structures

Details Method for forming dual damascene structures Method for forming dual damascene structures

1998-08-21

2001-03-20

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S625000, C438S688000, C438S642000, C438S656000

Reexamination Certificate

active

06204166

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor processing methods for imparting electrical contacts and multi-level electrical interconnection to integrated circuits.
BACKGROUND OF THE INVENTION
In the manufacture of ultra large scale integrated circuits (ULSI), such as 4 megabit and up dynamic random access memories (DRAMs), one approach is to use an inlaid wiring technology known in the art as “Dual Damascene” technology, as described in Kaanta, C. W., et al., “Dual Damascene: A ULSI Wiring Technology,” IBM General Technology Division, Essex Junction, Vermont,
VMIC Conference,
Jun. 11-12, 1991, pp. 144-152.
One Dual Damascene process utilizes first and second successive etching steps in order to arrive at a trough and via geometry within a surrounding insulating layer formed on the surface of a silicon wafer. The first etch step forms a trough which extends down to a controlled depth within the insulating layer. The second etch step extends the depth of the trough down to the active devices within the silicon substrate to form the via.
Another Dual Damascene process utilizes a first etch step to form a via through the insulating layer to the active devices within the substrate. To form the trench, a second layer of resist is then patterned over the insulating layer leaving the via exposed. The insulating layer is again etched, although not completely, thereby creating a trench in the insulating layer but no additional contacts to the substrate.
In each of the above Dual Damascene processes, after formation of the via and trench geometry a layer of conductive material is then blanket deposited over the surface of the insulating layer, and the wafer is planarized to leave conductive material within the via and trench.
Various problems are associated with the processes described above. One problem arises because the insulating layer is first etched to completely, or partially, form the via and then a second patterned resist layer is formed and the insulating layer is again etched. The subsequent etch results in the formation of non-volatile carbon-based debris in the bottom of the via. Due to the small size of the via, it is very difficult to completely remove the debris, and thus the conductive material which contacts the active device within the substrate may not make adequate electrical contact. In addition, two-step via fabrication processes, wherein the via is partially completed with the first etch, and then fully etched to expose the substrate during a subsequent trough etch, are inherently prone to producing non-uniform vias.
An approach to avoiding the above problems is to first etch a via to expose the substrate below a first insulating layer, then deposit and planarize a first metal layer to form a metal plug to the substrate. A second insulating layer having a trench is then patterned over the first metal layer and the first insulating layer. Next, a second metal layer is formed over the second insulating layer and then planarized. This approach, however, requires the formation and planarization of two insulating layers and two metal layers, thus adding multiple additional steps and an additional metal-to-metal interface, which also can be difficult to form reliably.
What is needed is a reliable and efficient Dual Damascene process, which provides uniform vias and avoids via debris and other problems which can result in inadequate electrical contact.
SUMMARY OF THE INVENTION
The present invention provides a process for forming vias and trenches for metalization and multi-level electrical interconnection in ULSI using a single metal deposition and a minimum of process steps for each interconnection.
According to the method of the invention, an insulator layer is deposited over a conductive substrate or device to be contacted. A via is then etched in the insulator layer to outwardly expose a surface of the conductive substrate. A non-photoreactive protective layer, preferably an organic anti-reflective coating, is then deposited in the via, followed by a photoreactive layer to pattern the line. A trench is then patterned and etched in the insulator layer and in communication with the via. The protective layer is then removed from the via, together with any residual debris resulting from the trench etch. A metal or other conductive material is then deposited in the via and trench, and then planarized.
The above process steps can be repeated to form multiple levels of via contacts and trough interconnects using a non-photoreactive layer to protect the via during the trench etch.


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Kaanta, Carter W., et al., Dual Damascene: A ULSI Wiring Technology, Jun. 11-12, 1991 VMIC Conference, pp. 144-152.

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