Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-08-09
2011-08-09
Vu, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S675000, C257SE21579
Reexamination Certificate
active
07994050
ABSTRACT:
A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.
REFERENCES:
patent: 5750587 (1998-05-01), Manzouji et al.
patent: 6583047 (2003-06-01), Daniels et al.
patent: 6638871 (2003-10-01), Wang et al.
patent: 6669858 (2003-12-01), Bjorkman et al.
patent: 6924228 (2005-08-01), Kim et al.
patent: 7241853 (2007-07-01), King et al.
patent: 7300597 (2007-11-01), Chae et al.
patent: 7309448 (2007-12-01), Chae et al.
patent: 2002/0081834 (2002-06-01), Daniels et al.
patent: 2002/0142586 (2002-10-01), Shiota
patent: 2002/0177070 (2002-11-01), Kozawa et al.
patent: 2004/0183203 (2004-09-01), Meagley et al.
patent: 2005/0029229 (2005-02-01), Chae et al.
patent: 2005/0124152 (2005-06-01), Meagley et al.
patent: 2005/0266691 (2005-12-01), Gu et al.
patent: 2006/0046467 (2006-03-01), Verhaverbeke
patent: 2006/0148243 (2006-07-01), Wang
patent: 2006/0183348 (2006-08-01), Meagley et al.
patent: 2007/0037396 (2007-02-01), Verhaverbeke
patent: 2007/0235684 (2007-10-01), Mistkawi et al.
patent: 2008/0268641 (2008-10-01), Lee et al.
patent: 1279603 (2006-10-01), None
patent: 735066 (1996-10-01), None
patent: 739945 (1996-10-01), None
patent: 842996 (1998-05-01), None
patent: 2005-72615 (2005-03-01), None
patent: 2005-315985 (2005-11-01), None
Heo Jung Gun
Lee Ki Lyoung
Hynix / Semiconductor Inc.
IP & T Group LLP
Taylor Earl N
Vu David
LandOfFree
Method for forming dual damascene pattern does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming dual damascene pattern, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming dual damascene pattern will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2620241