Method for forming dual-damascene interconnect structure

Details Method for forming dual-damascene interconnect structure Method for forming dual-damascene interconnect structure

2001-05-31

2003-02-25

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S725000

Reexamination Certificate

active

06524962

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for forming a dual-damascene structure, and more particularly relates to a method for forming a Cu/low-k dual-damascene structure.
2. Description of the Prior Art
In very and ultra large scale integration (VLSI and ULSI) circuits, an insulating or dielectric material, such as silicon oxide, of the semiconductor device in the dual damascene process is patterned with several thousand openings for the conductive lines and vias which are filled with metal, such as aluminum, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel signal lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrate on which semiconductor devices are mounted.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings also are formed. In the standard dual damascene process, the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via openings and the pattern is anisotropic etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with a resist material which is exposed to a second mask with the image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and grooves are filled with metal. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps.
As the dimensions of integrated circuits continues to shrink, Cu/low-k (k<3.0) integration scheme is the key point of reducing the RC delay and achieving the high performance interconnection. Copper can effectively reduce the electrical resistance of the conducting lines, and low-k dielectrics can decrease the capacitance between intra-metal lines. Spin-on-dielectrics (SOD) is the most potential process for the mass-production applications. They consist of aromatic thermosets polymers, and so on. The carbon contains a porous structure which will reduce the dielectric constant of the dielectrics. Usually, the mechanical strength of low-k dielectrics is much less than the conventional silicon dioxide as the increasing of carbon contains and porous ratio. Therefore, there are many challenges for Cu/low-k integration, especially for those ultra-low-k materials (k<2.5) having poor mechanical properties. How to form the dual-damascene structure is still a challenge for integrated circuits.
SUMMARY OF THE INVENTION
An object of the invention is to provide a method for forming a dual-damascene structure.
Another object of the invention is to provide a method for forming a dual-damascene structure in a Cu/low-k process.
In order to achieve the previous objects of the invention, the present method comprises the following steps. First, a substrate is provided. Then, a first low-k dielectric layer and a second low-k dielectric layer are sequentially formed on the substrate. Next, a first via hole is formed in the first low-k dielectric layer by removing a portion of the second low-k dielectric layer and the first low-k dielectric layer. Thereafter, a second via hole is formed in the second low-k dielectric layer by removing a portion of the second low-k dielectric layer, wherein the second via hole connects with the first via hole. Then, a conductive layer is formed to fill the first via hole and the second via hole. Next, the second low-k dielectric layer is removed. Last, a low-k dielectric layer is formed on the first low-k dielectric layer and exposes the conductive layer.


REFERENCES:
patent: 6114233 (2000-09-01), Yeh
patent: 6255735 (2001-07-01), Wang et al.
patent: 6265780 (2001-07-01), Yew et al.
patent: 6319814 (2001-11-01), Tsai et al.
patent: 6355555 (2002-03-01), Park
patent: 6380091 (2002-04-01), Wang et al.

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