Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-04-25
2003-01-14
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S624000, C438S761000, C438S763000, C438S778000, C438S784000
Reexamination Certificate
active
06506690
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to dielectric layer formation, such as that used for fabricating semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductor devices comprise layers of materials such as dielectrics and metals. Continued adherence of adjacent layers is important for device reliability and performance. If stress is present at layer interfaces peeling may occur during manufacturing processes or device utilization. For example, in the manufacture of semiconductor devices, high density plasma oxide (HDP) may be deposited on phosphosilicate glass (PSG). Subsequent etching of the layers sometimes results in the HDP peeling from the PSG, particularly in areas having a high density of windows and lines.
The SEM wafer cross-section in
FIG. 1
shows a partially manufactured semiconductor device exhibiting peeling at a PSG/HDP interface. Prior to deposition of the PSG on the HDP layer, a flow stabilization step was performed. Tetraethylorthosilicate (TEOS), O
2
and He were stabilized in the presence of a triethylphosphate (TEPO) flow. TEPO was used as a doping source in the subsequent PSG deposition step. A window was then etched through the PSG layer and into the HDP layer. Ti/TiN was deposited on the PSG surface and within the window. The wafer underwent a hydrofluoric acid etch in a 100:1 solution of H
2
O to HF. Location A on
FIG. 1
shows a separation or peeling of the PSG layer from the HDP layer. It can be seen in
FIG. 1
at location B that a lip has formed between the two layers. This lip formation provides a weak area that may be more prone to etchant attack in subsequent etching processes and thus facilitates peeling.
The PSG peeling from the HDP layer is likely to occur when phosphorus doping source TEPO deposits thermally during the flow stabilization step prior to PSG deposition. The purpose of the flow stabilization step is to allow the flow meter, which regulates the phosphorous flow, to stabilize prior to the deposition step. During flow stabilization phosphorous flow may go beyond or fall below an optimum amount. When the phosphorous overshoots the optimum concentration, i.e. when a flow spike occurs, an unintended thermally deposited layer is generated which contains phosphorus concentrations of about 20 to 30 weight percent. This highly concentrated phosphorus-containing layer etches faster than the intended phosphorus-containing layer which may lead to peeling. Furthermore, the space between the HDP and PSG layers created by the peeling may disadvantageously fill with subsequently deposited layers such as tungsten which may lead to device failure.
Attempts to remedy the peeling process include pumping TEPO out of the deposition system through a bypass valve normally present within the deposition apparatus, to eliminate unwanted thermally-deposited phosphorus during the flow stabilization step. However, when utilized in this manner, the bypass valve is prone to clogging and failure. When the bypass valve fails, the concentration of TEPO in the deposition chamber may cause thermal deposition, and hence peeling.
Therefore, it is desirable to have a process wherein unwanted thermally deposited material is reduced or eliminated without adverse effects to process equipment.
SUMMARY OF THE INVENTION
Peeling of a PSG layer from an HDP layer has been substantially eliminated by introducing an undoped dielectric layer between the PSG and HDP layers. By doing so, a flow stabilization process step implemented in conventional methods prior to PSG deposition may be eliminated. Further eliminated is bypass valve usage to pump TEPO from the deposition chamber, thereby avoiding problems associated with bypass valve failure.
In one embodiment a wafer is provided having an HDP layer. An undoped silicon glass layer is deposited on top of the HDP layer which improves adherence of a subsequently deposited PSG layer. A further embodiment includes creating a substantial vacuum in a deposition chamber after deposition of the PSG layer and thereafter filling the chamber with an inert gas. The inert gas purges the deposition chamber of residual gases. A vacuum is again drawn in the deposition chamber to substantially remove the inert gas.
Embodiments of the invention may be applied to dielectric layers other than PSG and HDP that exhibit peeling or other interface weaknesses when disposed upon one another. An intermediary dielectric layer is disposed between two dielectric layers thereby eliminating a flow stabilization step that may produce unwanted deposition that leads to peeling.
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patent: 6153512 (2000-11-01), Chang et al.
patent: 6153537 (2000-11-01), Bacchetta et al.
patent: 6165915 (2000-12-01), Jang
Wolf, S., Silicon Processing for the VLSI Era, 1990, Lattice Press, vol. 2: Process Integration, p. 196.
Agere Systems Inc.
Lytle Craig P.
Smith Matthew
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