Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-01-02
2003-05-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S424000, C438S433000
Reexamination Certificate
active
06569750
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a device isolation film for a semiconductor device and, in particular, to an improved method for forming a device isolation film that can prevent degradation of a gate electrode formed at the intersection of the trench type device isolation film and an active region in a subsequent process. The improved method provides for forming an impurity region at the side walls of a trench by ion-implanting an impurity into a semiconductor substrate at both sides of the trench.
2. Description of the Background Art
In order to improve the degree of integration of a device, it is generally necessary to reduce the dimensions of each component in a device and the width and area of the device isolation regions that separate the devices. The device isolation region occupies a large area in a memory cell. Accordingly, the reduction of the size of the memory cell depends on the degree to which the size of the device isolation region can be reduced.
Methods for forming device isolation films have included the local oxidation of silicon (LOCOS), the poly-buffed LOCOS (PBL) method which involves sequentially stacking an oxide film, a polysilicon layer and a nitride film on a silicon substrate, and the trench method which involves forming a groove in the substrate and filling the groove with an insulating material.
FIGS. 1
a
and
1
b
are cross-sectional diagrams illustrating sequential steps of a conventional method for forming a trench type device isolation film for a semiconductor device.
As illustrated in
FIG. 1
a,
a pad oxide film
13
and a pad nitride film
15
are formed on a semiconductor substrate
11
at a predetermined thickness.
The pad nitride film
15
, the pad oxide film
13
and a predetermined thickness of the semiconductor substrate
11
are then etched according to a photolithography process using a device isolation mask (not shown), thereby forming a trench
17
.
The trench
17
is then filled with an oxide film
19
. The oxide film
19
is initially formed over the entire structure, and then planarized, preferably using a CMP process.
As depicted in
FIG. 1
b
, after the device isolation oxide film is formed, the pad nitride film
15
and the pad oxide film
13
are removed. A well (not shown) is then formed by ion-implanting an impurity into the semiconductor substrate
11
.
A gate oxide film
21
is then formed on the surface of the semiconductor substrate
11
in the active regions. A gate electrode is then formed on the gate oxide film
21
, in this instance having a stacked structure with layers of a doped polysilicon
23
and a tungsten silicide
25
.
The gate electrode is also formed on the device isolation film, i.e. the non-active region at the same time it is formed in the active region. Furthermore, a moat is formed between the active region and the non-active region.
The indicated regions â denote a portion where an inverse narrow width effect is generated due to a decreased dopant concentration.
Referring to
FIGS. 2 and 3
, the device isolation film shows how the inverse narrow width effect decreases the channel width and thus reduces the threshold voltage.
In this case, the dopant in the channel region has moved to the trench, thereby causing the inverse narrow width effect. The channel concentration can be increased to overcome this disadvantage. However, the increased channel doping, however also increases the leakage current, thereby degrading the a refresh properties of the resulting device.
In addition, the gate electrode formed at the upper portion of the moat of the trench tends to have a reduced thickness, as compared with the general active region, and thus the threshold voltage is decreased.
As described above, the inverse narrow width effect decreases the threshold voltage of the transistor, increases the leakage current of the cell, and thus degrades the refresh properties. On the other hand, as dopant moves to the trench, the accumulation causes a short channel hump phenomenon at the trench. That is, a parasitic transistor is created at the sidewalls of the trench, thereby increasing the offstate leakage current.
As a result, the conventional method for forming the device isolation film for the semiconductor device generates the inverse narrow width effect, thereby increasing the leakage current of the device and degrading the device refresh properties thereof. Thus, the performance and reliability of the resulting semiconductor devices are weakened.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method for forming a device isolation film for a semiconductor device which can prevent degradation devices properties and improve reliability of the resulting semiconductor devices, with an impurity implantation region. This impurity implantation region is formed by ion-implanting an impurity into the semiconductor substrate at both sides of the intended trench location before the trench etching process.
In order to achieve the above-described object a method is provided for forming a device isolation film for a semiconductor device, including the steps of: sequentially forming a pad oxide film and a pad nitride film on a semiconductor substrate; forming a pad oxide film pattern and a pad nitride film pattern, by patterning and etching the pad oxide film and the pad nitride film using a device isolation mask; forming an impurity implantation region by ion-implanting an impurity into the semiconductor substrate using the pad nitride film pattern as a mask, and by diffusing the implanted impurity with a thermal treatment; forming a trench by etching the semiconductor substrate again using the pad nitride film pattern as a mask, the impurity implantation region being provided at the sidewalls of the trench; forming a device isolation film filling the trench, and removing the pad nitride and pad oxide; and forming a gate electrode on the device isolation film and active region, the impurity implantation region being located in the semiconductor for substrate beneath at least a portion of the gate electrode.
REFERENCES:
patent: 5904538 (1999-05-01), Son et al.
patent: 5943585 (1999-08-01), May et al.
patent: 6001707 (1999-12-01), Lin et al.
patent: 6030882 (2000-02-01), Hong
patent: 6165871 (2000-12-01), Lim et al.
patent: 6300655 (2001-10-01), Ema et al.
patent: 60-140754 (1985-07-01), None
Jeong Jae Goan
Kim Young Seok
Hyundai Electronics Industries Co,. Ltd.
Isaac Stanetta
Niebling John F.
Pillsbury & Winthrop LLP
LandOfFree
Method for forming device isolation film for semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming device isolation film for semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming device isolation film for semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3047159